Vertical memory device and method of manufacturing the same

Abstract

Disclosed are vertical memory devices and methods of manufacturing the same. The vertical memory device may include includes a substrate, a gate stack structure and channel structure on the substrate, and a charge trap structure between the gate stack structure and the channel structure. The gate stack structure includes conductive structures and insulation interlayer structures that are alternately stacked on each other in a vertical direction on the substrate such that cell regions and inter-cell regions are alternately arranged in the vertical direction. The channel structure penetrates through the gate stack structure in the vertical direction. The charge trap structure and the conductive structures define memory cells at the cell regions. The charge structure is configured to selectively store charges. The charge trap structure includes an anti-coupling structure in the inter-cell region for reducing a coupling between neighboring memory cells adjacent to each other in the vertical direction.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]This application claims priority under 35 U.S.C §119 to Korean Patent Application No. 10-2016-0095738 filed on Jul. 27, 2016 in the Korean Intellectual Property Office, the contents of which are incorporated by reference herein in their entirety.BACKGROUND1. Field[0002]Example embodiments relate to a vertical memory device and a method of manufacturing the same, and more particularly, to a vertical NAND flash memory device and / or a method of manufacturing the same.2. Description of Related Art[0003]A vertical NAND flash memory device in which a plurality of memory cells is vertically stacked on a substrate has been proposed for increasing memory capacity of the NAND memory devices.[0004]As the vertical NAND flash memory device tend to be downsized together with high stack density of the memory cells, the electron diffusion and the cross talk occurs much more frequently between the vertically neighboring stack cells, which affect the relia...

AI Technical Summary

Benefits of technology

The present invention provides a vertical memory device with increased trap density and reduced cross talk between neighboring cells in the inter-cell region. This is achieved by increasing the charge trap pattern and dielectric inter-cell pattern. Additionally, an anti-coupling structure is provided to reduce coupling between adjacent cells and improve the device's operation reliability and stability. The charge trap structure may have first and second patterns that are separated in the inter-cell region to prevent electron diffusion and increase the charge density in the cell region. The anti-coupling structure may be indented into the inter-cell recess and has a smaller dielectric constant than the first and second patterns, which further reduces the coupling between cells.

Problems solved by technology

Accordingly, the trap density in the charge trap pattern is not sufficient each cell of the vertical NAND flash memory device, which makes the memory window size of the flash memory device very variable and unstable in response to the size of the flash memory device.

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