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High voltage junction field effect transistor

a high-voltage junction and transistor technology, applied in the field of semiconductor devices, can solve the problems of easy slipping of the voltage, and achieve the effect of reducing the sensitivity to process variation

Active Publication Date: 2017-01-05
MACRONIX INT CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The invention simplifies the design of the HVJFET to reduce sensitivity to process variation by replacing the well region with a shallower doping depth. Additionally, the first doped region, which also partially overlaps with the second doped region, serves as the pinch off channel to stabilize the electrical properties. The invention also includes one or more secondary doped regions to adjust the drain current. These changes make the HVJFET more robust and reliable.

Problems solved by technology

However, the traditional HVJFET requires a well region so as to pinch off voltage and the well is more sensitive to the process variation.
As a result, the pinch off voltage may shift easily.

Method used

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Examples

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first embodiment

[0037]FIG. 1 is a schematic top view of a semiconductor device according to the invention.

[0038]With reference to FIG. 1, the invention provides a semiconductor device 1, which includes: a substrate 100, a well region 102 of a first conductivity type, a plurality of top doped regions 116 of a second conductivity type, a first doped region 110 of the first conductivity type, a field region 104 of the second conductivity type, and a second doped region 112 of the second conductivity type. The substrate 100 is a semiconductor substrate of the first conductivity type, e.g., a P-type substrate, for example. A material of the semiconductor substrate is at least one selected from a group consisting of Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC, InAs, and InP, for example. The substrate 100 may also be an EPI layer, a non-EPI layer, a silicon on insulator (SOI) substrate, or a combination of the foregoing, for example.

[0039]The well region 102 is located in the substrate 100. Although FIG. 1 illus...

second embodiment

[0043]FIG. 2 is a schematic top view of a semiconductor device according to the invention.

[0044]With reference to FIG. 1 and FIG. 2, a semiconductor device 2 of the second embodiment is similar to the semiconductor device 1 of the first embodiment of the invention, and a difference therebetween lies in that: the semiconductor device 2 of the second embodiment includes two field regions 104a and 104b, two second doped regions 112a and 112b, two third doped regions 114a and 114b, two top doped regions 106a and 106b, and two fourth doped regions 124a and 124b. In FIG. 2, the field regions 104a and 104b, the second doped regions 112a and 112b, the third doped regions 114a and 114b, the top doped regions 106a and 106b, and the fourth doped regions 124a and 124b are arranged symmetrically with respect to the first doped region 110. Nevertheless, the invention is not limited thereto. In other embodiments, the foregoing doped regions are arranged asymmetrically with respect to the first dop...

third embodiment

[0045]FIG. 3 is a perspective cross-sectional view of a semiconductor device according to the invention. FIG. 4 is a schematic cross-sectional view along the line A-A′ of FIG. 3. FIG. 5 is a schematic cross-sectional view along the line B-B′ of FIG. 3.

[0046]With reference to FIG. 3, FIG. 4, and FIG. 5, the invention provides a semiconductor device 3, which includes: a substrate 100 of a second conductivity type, a well region 102 of a first conductivity type, a field region 104 of the second conductivity type, a first doped region 110 of the first conductivity type, a second doped region 112 of the second conductivity type, a third doped region 114 of the first conductivity type, a top doped region 106 of the second conductivity type, and an insertion layer 108 of the first conductivity type. The material of the substrate 100 has been specified in the above embodiment and thus is not repeated hereinafter.

[0047]The well region 102 is located in the substrate 100. In an embodiment, a ...

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Abstract

Provided is a semiconductor device, including: a substrate, a well region of a first conductivity type, a field region of a second conductivity type, a first doped region of the first conductivity type, and a second doped region of the second conductivity type. The well region is located in the substrate. The field region is located in the well region. The first doped region is located in the well region of a first side of the field region. The second doped region is located in the field region, wherein the first doped region is at least partially surrounded by the second doped region.

Description

BACKGROUND OF THE INVENTION[0001][Field of the Invention][0002]The invention relates to a semiconductor device and particularly relates to a high voltage junction field effect transistor (JFET).[0003][Description of Related Art][0004]High voltage devices are extensively used in power management integrated circuits (PMIC), switch mode power supplies (SMPS), and LED drivers. In recent years, green energy technology, which requires higher conversion efficiency and lower standby power consumption, is drawing more and more attention. Generally, a start-up circuit and a pulse width modulation (PWM) circuit are integrated in a switch mode power integrated circuit. The start-up circuit can be used for starting up the pulse width modulation circuit and is turned off when the pulse width modulation circuit is started up and begins to operate. Thus, the start-up circuit needs to have the characteristic of low leakage current.[0005]Compared to the conventional power resistor or high voltage dep...

Claims

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Application Information

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IPC IPC(8): H01L29/808H01L29/06H01L29/10
CPCH01L29/0692H01L29/1066H01L29/808H01L29/0649H01L29/0634H01L29/66901H01L29/1095H01L29/063H01L29/66893H01L29/7832
Inventor CHAN, WING-CHORWU, HSING-CHIH
Owner MACRONIX INT CO LTD
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