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Semiconductor device and method of manufacturing the same

a semiconductor and semiconductor technology, applied in the direction of semiconductor devices, semiconductor/solid-state device details, electrical equipment, etc., can solve problems such as product stress at a problematic level, bump crack or chip crack, etc., and achieve the effect of reducing stress and stress

Inactive Publication Date: 2013-05-16
RENESAS ELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The present invention provides a semiconductor chip that can reduce stress when there is a difference in the density of bumps. This is achieved by creating a third region with a higher area density to reduce stress at the time of mounting the chip on a wiring board. The method of manufacturing the semiconductor device includes preparing a wiring board and a semiconductor chip with bumps, and mounting the chip on the wiring board by heat treatment to face the electrode terminal group. The technical effect of this invention is to reduce the risk of bump crack and chip crack due to stress.

Problems solved by technology

Such stress may cause a bump crack or a chip crack.
Apparently, there is a problem that stress at a problematic level for a product occurs when the arrangement of the bumps 101 has a notable density difference as shown in FIG. 3.

Method used

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  • Semiconductor device and method of manufacturing the same
  • Semiconductor device and method of manufacturing the same
  • Semiconductor device and method of manufacturing the same

Examples

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first embodiment

[0029]A first embodiment according to the present invention will be described with reference to the drawings. FIG. 4 is a cross-sectional view showing a semiconductor device according to the present embodiment.

[0030]As shown in FIG. 4, the semiconductor device of the present embodiment includes a wiring board and a semiconductor chip 13. The wiring board 1 has a chip mounting surface 12. On the chip mounting surface 12, multiple electrode terminals 5 are formed as an electrode terminal group. Meanwhile, the semiconductor chip 13 includes a chip substrate 2 having a semiconductor integrated circuit formed thereon. The chip substrate 2 is provided with a bump formation surface 7. Multiple bumps 3 are formed on the bump formation surface 7 as a bump 3 group. The semiconductor chip 13 is mounted on the wiring board 1 so that the bump formation surface 7 would face the chip mounting surface 12. An arrangement pattern of the bumps 3 on the bump formation surface 7 is the same as an arrang...

second embodiment

[0044]Next, a second embodiment will be described. FIG. 8 shows a bump formation surface 7 of a semiconductor device according to the second embodiment. In the present embodiment, the size and the arrangement of bumps 3 in a third region 11 are different from those in the first embodiment. The other points may be the same as the first embodiment, and thus the detailed description thereof is omitted here.

[0045]In the present embodiment, as in the case of the first embodiment, the region of the third region 11 having the bumps 3 arranged thereon has an area density (third density) which is higher than a second density and is lower than a first density. However, in the present embodiment, the number of the bumps 3 arranged per unit area in the third region 11 is the same as that in the second region 10. Meanwhile, the size of each of the bumps 3 arranged in the third region 11 is larger than the size of each of the bumps 3 arranged in the first region 9 and the second region 10. Note t...

third embodiment

[0050]Next, a third embodiment of the present invention will be described. FIG. 10 shows a bump formation surface 7 of a semiconductor device according to the third embodiment. In the present embodiment, a bump group provided on the bump formation surface 7 includes actual bumps 3-1 and dummy bumps 3-2. The other points maybe the same as the above-described embodiments, and thus the detailed description thereof is omitted here.

[0051]The actual bumps 3-1 are bumps used for electrical connection between a semiconductor chip 13 and a wiring board 1. On the other hand, the dummy bumps 3-2 are provided to control the area density of a region where the bumps are arranged, and are not used for the electrical connection between the semiconductor chip 13 and the wiring board 1.

[0052]According to the present embodiment, the stress can be reduced by the same effects as the above-described embodiments. In addition, the area density of a region where the bumps 3 are arranged can be controlled by...

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Abstract

A semiconductor device includes a wiring board, a semiconductor chip mounted on the wiring board, the semiconductor chip including a bump formation surface, a plurality of first bumps provided within a first region of the bump formation surface, the first bumps being arranged in a first area density, a plurality of second bumps provided within a second region of the bump formation surface, the second bumps being arranged in a second area density, and a plurality of third bumps arranged between the first region and the second region of the bump formation surface in a two-dimensional array. The plurality of third bumps are arranged in a third area density being higher than the second area density and being lower than the first area density.

Description

INCORPORATION BY REFERENCE[0001]The present application is a Continuation application of U.S. patent application Ser. No. 12 / 588,394, filed on Oct. 14, 2009, which is based and claims priority from Japanese Patent Application No. JP 2008-293191, filed on Nov. 17, 2008, the entire contents of which is incorporated herein by reference.BACKGROUND OF THE INVENTION[0002]1. Field of the Invention[0003]The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device.[0004]2. Description of the Related Art[0005]A semiconductor package (a semiconductor device) includes a semiconductor chip and a wiring board on which the semiconductor chip is mounted. The semiconductor chip is provided with a bump formation surface on which protruding bumps are formed. Solder, for example, is used as a material for the bumps. The semiconductor chip is mounted on the wiring board by using the bump formation surface.[0006]In such a semiconductor device, stress is a...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): H01L23/498
CPCH01L23/49838H01L24/17H01L2224/0401H01L2224/0603H01L2224/13099H01L23/49811H01L2924/01077H01L2924/14H01L24/13H01L2924/01006H01L2924/01033H01L2224/1403H01L2224/14
Inventor TAKEDA, KUNIHIRO
Owner RENESAS ELECTRONICS CORP
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