Magnetoresistive sensor with reduced parasitic capacitance, and method
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[0036]FIG. 2 is a schematic illustration of an ASIC (application-specific integrated circuit) chip 50, carrying an ASIC 45 for reading and / or electrical biasing of one or more magnetoresistive elements. The ASIC 45 is of a type integrated in a semiconductor substrate 30, and is configured for carrying out reading and / or electrical biasing of magnetoresistive elements in a magnetic-field sensor, of the AMR type. In particular, as described in detail with reference to FIG. 5, said magnetic-field sensor is obtained by assembling together the ASIC chip 50 and a further chip 60, distinct from the ASIC chip 50, carrying the magnetoresistive elements (FIG. 3).
[0037]The ASIC chip 50 comprises, according to an embodiment of the present disclosure, a first element 32 and a second element 34 for generation of magnetic fields. According to one embodiment, the first and second magnetic field generators 32, 34 are formed by a conductive element configured for being traversed by electric current. ...
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