Phase-locked loop circuit comprising voltage-controlled oscillator having variable gain

Abstract

A phase-locked loop (PLL) circuit including a voltage-controlled oscillator (VCO) with a variable gain is provided. A phase frequency detector (PFD) detects a phase difference between a reference signal and a PLL feedback signal. A charge pump and a loop filter sequentially process an output signal of the PFD. A VCO has different gains according to a mode transition. A control voltage applied to the VCO is selected from an output signal of the loop filter and an additional control signal according to the mode transition.

Description

CROSS-REFERENCE TO RELATED APPLICATION[0001]This application claims priority to and the benefit of Korean Patent Application No. 10-2009-0128042, filed Dec. 21, 2009, and Korean Patent Application No. 10-2010-0032656, filed Apr. 9, 2010, the disclosure of which is incorporated herein by reference in its entirety.BACKGROUND[0002]1. Field of the Invention[0003]The present invention relates to a phase-locked loop (PLL) circuit including a voltage-controlled oscillator (VCO) having a variable gain and, more particularly, to a PLL circuit in which a VCO has different gains according to a mode transition to ensure a wide operating frequency and improve a phase noise characteristic.[0004]2. Discussion of Related Art[0005]In general, a phase-locked loop (PLL) circuit is a frequency feedback circuit configured to generate a signal having an arbitrary frequency in response to the frequency of an externally applied signal. The PLL circuit may detect a phase difference between a reference signa...

AI Technical Summary

Benefits of technology

[0009]The present invention is directed to a phase-locked loop (PLL) circuit in which a voltage-controlled oscillator (VCO) has different gains according to a mode transition so that the PLL circuit may ensure a wide operating frequency and an improved phase noise characteristic.

[0010]Also, the present invention is directed to a PLL circuit configured to increase a tuning range without increasing the number of capacitor banks to reduce a designed area and improve the performance of the entire circuit.

Problems solved by technology

That is, as the power supply voltage of the PLL circuit decreases, a tuning range of the PLL circuit may be further limited.

However, when the number of the capacitor banks is increased, the entire designed area may be increased, and a VCO may exhibit a nonlinear characteristic according to the number of capacitor banks.

Also, when a large number of capacitor banks are provided, a parasitic capacitor and a leakage current may be caused to the output of the VCO, thereby reducing a Q-value.

Meanwhile, when the number of inductors is increased, the designed area may be limited, and the use of the VCO with a large gain may worsen noise characteristics of the PLL circuit.

That is, when the VCO has a great gain, the frequency of the VCO may be greatly varied due to noises of the control voltage of the PLL circuit, thereby adversely affecting the noise characteristics of the PLL circuit.

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