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Gated Diode Memory Cells

a diode memory and gate technology, applied in the field of memory cells, can solve problems such as voltage drop in the cell

Inactive Publication Date: 2011-02-03
GLOBALFOUNDRIES INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0011]A gated diode memory cell is provided, including one or more transistors, such as field effect transistors (“FETs”), and a gated diode in signal communication with the FETs such that the gate of the gated diode is in signal communication with the source of a first FET, wherein the gate of the gated diode forms one terminal of the storage

Problems solved by technology

This means that there is a voltage drop in the cell during a Read operation.

Method used

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Embodiment Construction

[0036]Traditionally, dynamic memory cells based on capacitors have exhibited voltage drops (such as 1T1C), or at best, a holding equal (such as 2T1C) during Read operations. A new memory cell is provided where the cell voltage can be increased during a Read operation, thereby significantly improving the sensing signal, sensing signal-to-noise ratio and sensing speed for dynamic memories built with cell structures according to the present disclosure. In the description that follows, the term “storage cell” refers to the gated diode, and the term “memory cell” refers to the whole 1T1D or the whole 2T1D device. The terms “implementing FET for the gated diode”, “gated diode implementing FET” or simply “gated diode FET” may be used interchangeably.

[0037]As shown in FIG. 1A, a Gated Diode Memory Gain Cell for a one-transistor one-diode (“1T1D”) DRAM cell is indicated generally by the reference numeral 110. The 1T1D DRAM cell 110 includes a transistor 112 in signal communication with a gat...

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Abstract

A gated diode memory cell is provided, including one or more transistors, such as field effect transistors (“FETs”), and a gated diode in signal communication with the FETs such that the gate of the gated diode is in signal communication with the source of a first FET, wherein the gate of the gated diode forms one terminal of the storage cell and the source of the gated diode forms another terminal of the storage cell, the drain of the first FET being in signal communication with a bitline (“BL”) and the gate of the first FET being in signal communication with a write wordline (“WLw”), and the source of the gated diode being in signal communication with a read wordline (“WLr”).

Description

CROSS-REFERENCE TO RELATED APPLICATION[0001]This is a Divisional Application of U.S. application Ser. No. 10 / 735,061 filed on Dec. 11, 2003, the disclosure of which is herein incorporated by reference in its entirety.BACKGROUND[0002]The present disclosure relates to dynamic random access memory (“DRAM”) and, more particularly, to memory cells and architectures with improved charging capabilities.[0003]As shown in FIG. 1A, a conventional one-transistor one-capacitor (“1T1C”) DRAM cell is indicated generally by the reference numeral 10. The 1T1C DRAM cell 10 includes a transistor 12 in signal communication with a capacitor 13. A corresponding plot of memory cell voltage (“V_cell”) versus time is indicated generally by the reference numeral 15. During a Read operation, when a memory cell is Read and connected to the bitline (“BL”), the charges are shared between the cell and the BL or discharged to the BL, and subsequently the steady-state cell voltage, which is the same as the BL volt...

Claims

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Application Information

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IPC IPC(8): G11C11/36
CPCG11C11/404G11C11/36
Inventor LUK, WING K.DENNARD, ROBERT H.
Owner GLOBALFOUNDRIES INC
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