Digital adjustment of an oscillator

Abstract

The invention concerns the adjustment of an oscillation frequency of an oscillator, in particular the digital coarse adjustment of a PLL oscillator by means of a circuit arrangement comprising at least one pair of capacitors (C, C′), of which first terminals are connected with the oscillator, and second terminals can selectively be connected by means of a switching arrangement with a first reference potential (vss), in order to incorporate the capacitor pair (C, C′) into an oscillating circuit of the oscillator, wherein the circuit arrangement comprises: first FETs (T1, T1′) for the respective connection of the second terminals with the first reference potential (vss), a second FET (T2) for the connection of the second terminals with each other, and third FETs (T3, T3′) for the respective connection of the second terminals with a second reference potential (vdd), which differs from the first reference potential (vss).

Description

BACKGROUND TO THE INVENTION / FIELD OF THE INVENTION [0001] The present invention concerns the adjustment of an oscillation frequency of an oscillator. In particular the invention concerns a circuit arrangement for a frequency adjustment of this kind as well as the use of a circuit arrangement of this kind. DESCRIPTION OF PRIOR ART [0002] It is of known art to alter or adjust the oscillation frequency of an oscillator comprising an electrical oscillating circuit by selectively introducing an electrical capacitance into the oscillating circuit. In the field of microelectronics the selective connection of such a capacitance can advantageously be accomplished by means of one or a plurality of field effect transistors, in what follows designated as “FET” or “FETs”. [0003] When using FETs for the selective connection (and disconnection) of (as necessary additional) capacitance in an oscillating circuit the problem ensues in practice, in particular if a very small capacitance is being conne...

AI Technical Summary

Benefits of technology

[0009] In the circuit arrangement according to the invention a capacitor pair can be introduced into the oscillating circuit of the oscillator, in that the first FETs are switched on and the second capacitor terminals are thus connected with the first reference potential. In order here to reduce the electrical resistance of the path introduced the second FET is provided, by means of which at the same time the second capacitor terminals can be connected with each other. Finally the third FETs can advantageously be used to reduce considerably the parasitic capacitances still active in the switched-off state of the first FETs and the second FET, in particular e.g. to reduce the source-substrate capacitance and the drain-substrate capacitance of the second FET, in that via the third FETs the potentials prevailing at the second capacitor terminals and thus at the source and drain terminals of the second FET are “shifted” in a manner such that the parasitic capacitances are reduced.

[0020] The above-mentioned high resistance connection, created by means of a third FET in its switched-on state, can in a simple manner be ensured by means of a channel length of sufficiently large dimensions, in what follows also designated as “L”, or by a small channel width, in what follows also designated as “W”. In particular in this case, however, the problem can arise that the switching on of the third FET takes place comparatively slowly. This prevents a rapid adjustment of the oscillator frequency, or delays the reduction of the parasitic capacitances provided according to the invention. To remove this problem in accordance with a further development of the invention provision is made that the switch arrangement comprises a further fourth FET in parallel to each of the third FETs. With a brief switching-on of the fourth FET during the switching-on of the related third FET the “switching-on time period” of the third FET can to a certain extent be bridged by the fourth FET that is connected in parallel. In particular this is then very effective if the W / L ratio of the fourth FET is larger than the W / L ratio of the third FET arranged in parallel with the former (e.g. larger by at least a factor 2). The brief switching-on of the fourth FETs during the switching-on of the third FETs can be accomplished by means of an appropriately designed control circuit, into which is / are inputted the one or more control signals for the switching of the first, second and third FETS, and which on the basis of this signal or signals generates a control signal for the control of the fourth FETs and applies it to the gate terminals of the fourth FETs. Such a control circuit can for example have a logic array device and a delay element, which defines the switching-on duration of the fourth FETs.

[0024] The use of the circuit arrangement according to the invention in a PLL oscillating circuit for clock extraction or recovery is very advantageous inasmuch as a large PLL capture range can thus be achieved with, at the same time, a small phase error (in particular so-called “jitter”) in the PLL output clock signal. In this connection the following is to be considered: A large capture range requires in very general terms a more or less rapid and large adjustability of the oscillation frequency, as could be implemented e.g. by a varactor of relatively large dimensions in the oscillating circuit of the PLL oscillator. However, when using a varactor that can be adjusted over a wide range disturbances such as noise in the oscillator part can be converted more or less efficiently into phase errors as phase noise in the PLL output signal, and so a varactor with large dimensions has a tendency to deteriorate the quality of the PLL output signal. This problem can be overcome by means of the invention in that in the PLL a coarse adjustment designed according to the invention is combined in a manner known per se with a fine adjustment implemented in a varactor to achieve a large PLL capture range with, at the same time, a small phase error. In order to achieve here a high quality factor for the connected capacitors or capacitances, favourable for the achievement of a small phase error, switching transistors that have channel widths of comparatively large dimensions can be used directly, since according to the invention the parasitic capacitances that thus have a tendency to increase in size are reduced by the configuration according to the invention. The result is the creation of a capacitor arrangement in which the parasitic capacitances are minimised, without any significant impairment of the quality factor of the oscillating circuit (e.g. “LC tank”), combined with a rapid switching time.

Problems solved by technology

When using FETs for the selective connection (and disconnection) of (as necessary additional) capacitance in an oscillating circuit the problem ensues in practice, in particular if a very small capacitance is being connected, that parasitic capacitances of a greater or lesser size are always present between the various terminals, including the substrate of an FET.

While these parasitic capacitances can indeed be taken into account in the design of a circuit arrangement used for the adjustment of the oscillation frequency, they disadvantageously reduce the adjustment range achievable with regard to the capacitance and accordingly with regard to the oscillation frequency.

This problem is all the more serious the larger the dimensions of the FET concerned (channel length and / or channel width).

Images