Ferroelectric memory transistor with conductive oxide gate structure

Abstract

The present invention discloses a ferroelectric transistor having a conductive oxide in the place of the gate dielectric. The conductive oxide gate ferroelectric transistor can have a three-layer metal / ferroelectric / metal or a two-layer metal / ferroelectric on top of the conductive oxide gate. By replacing the gate dielectric with a conductive oxide, the bottom gate of the ferroelectric layer is conductive through the conductive oxide to the silicon substrate, thus minimizing the floating gate effect. The memory retention degradation related to the leakage current associated with the charges trapped within the floating gate is eliminated. The fabrication of the ferroelectric transistor by a gate etching process or a replacement gate process is also disclosed.

Description

RELATED APPLICATIONS [0001] This application is a Continuation of a pending patent application entitled, CONDUCTIVE METAL OXIDE GATE FERROELECTRIC MEMORY TRANSISTOR, invented by Hsu et al., Ser. No. 10 / 659,547, filed Sep. 9, 2003, Attorney Docket SLA0746, which is incorporated herein by reference.FIELD OF THE INVENTION [0002] This invention related generally to semiconductor device and nonvolatile memory transistor, and more particularly to ferroelectric gate transistor structures and methods of fabrication. BACKGROUND OF THE INVENTION [0003] Ferroelectric materials are composed of many randomly-distributed permanently polarized regions. When an electric field is applied, the regions with a polarization component in the direction of the electric field grow at the expense of the non-aligned regions so that a net polarization can result. If the electric field decreases, the polarization also decreases but at a slower rate so that even when the electric field becomes zero, a remnant po...

AI Technical Summary

Benefits of technology

[0012] The present invention discloses a ferroelectric transistor having a conductive oxide in the place of the gate dielectric. By replacing the gate dielectric with a conductive oxide, the bottom gate of the ferroelectric layer is conductive through the conductive oxide to the silicon substrate, therefore there is no floating gate effect. The memory retention degradation related to the leakage current associated with the charges trapped within the floating gate is eliminated. Furthermore, the operating voltage for the ferroelectric transistor can be reduced to the ferroelectric layer programming voltage because of the absence of the gate dielectric.

[0015] The conductive oxide further can have the advantages of possible lattice matching with the ferroelectric layer, reducing or eliminating the oxygen diffusion problem at the ferroelectric interface to improve the reliability of the ferroelectric transistor, and possible etch selectivity improving with other dielectric and metal films.

Problems solved by technology

However, effective transistor operation of the above MFS transistor is difficult to achieve due to the requirement of the ferroelectric / silicon interface.

When a ferroelectric film is deposited directly on the silicon substrate, metals and oxygen from the ferroelectric layer may diffuse into the ferroelectric-silicon interface, creating interface trap charges, affecting the polarization of the ferroelectric film, and overall may make the operation of the ferroelectric transistor becoming unstable.

Further, since the thermal expansion coefficient and lattice structure of a ferroelectric film is not compatible with silicon, it is very difficult to form a high-quality ferroelectric film with a clean interface directly on the silicon substrate.

However, they incorporate other difficulties such as higher operation voltage and trapped charges in the bottom floating gate layer.

This additional resistor ensures that the potential of the floating gate will approach that of the source / drain region after a certain delay time, but this could affect the high speed switching characteristics of the ferroelectric memory.

In either designs, the higher operation voltage issue still remains due to the presence of the gate dielectric.

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