Code generator for finite state machines

Abstract

The present invention relates to a method for automatically generating HDL code, a code generator and a product for generating the code for the purpose of its implementation in programmable logic, based on a graphical representation for coding a state machine. With the method according to the invention, state transitions are executed on the basis of a modified query structure in that, starting from a target state, all the preconditions are derived which must be fulfilled in order to reach said target state.

Description

CROSS REFERENCE TO RELATED APPLICATIONS[0001]This application claims priority of German application No. 10 2006 010 534.6 filed Mar. 7, 2006, which is incorporated by reference herein in its entirety.FIELD OF THE INVENTION[0002]The invention relates to a method, a device and a product for a code generator for describing finite state machines in a hardware description language for the purpose of their implementation in hardware.BACKGROUND OF THE INVENTION[0003]State machines (or finite state machines, as they are also called) can be defined as self-contained systems having a set of “states” and certain “transitions” between these states. They are often used in the design of digital circuits. There are a number of development tools on the market for implementing state machines in programmable logic (such as e.g. PLDs, CPLDs or FGPAs). State machines can be divided into two classes according to the type of result or, as the case may be, output they yield. On the one hand there are Moor...

AI Technical Summary

Benefits of technology

[0010]The object of the present invention is therefore to reveal a way in which the generated hardware code can be improved, in particular in respect of synthesis, execution time and area, and in particular can be designed more efficiently, and in which the generated code is free of syntactical errors and is unique.

[0016]In the preferred embodiment, processing of internal intermediate signals is dispensed with to the greatest possible extent. This has the advantage that the respective section containing the signal declarations in the previous code (i.e. the code generated using the existing prior art code generators) is substantially longer than the corresponding section in the case of the code generated by means of the method according to the invention.

[0017]In the hardware development too, all preliminary phases for generating programmable are basically subjected to a check to verify freedom from error. An important factor in the error check is to be seen in the clearly organized structure of the code. When using case state vectors it is possible to generate a clearly structured code. The inventive solution also exploits this advantage in an advantageous development by also representing in addition the case state vector typically used previously. An important characteristic in this arrangement is, however, that the case state vector is represented only in a symbolic manner in the generated code. This can be for example in the form of a comment which, though being generated, is not taken into account any further during the subsequent synthesis. It can only be used within the framework of the simulation. This advantageously leads to easier debugging compared to a code generated according to the invention which does not include the case state vector or the state vector. By using the state vector only during the simulation and not in the subsequent synthesis it is advantageously possible that no additional gates need to be generated.

[0018]During the code generation process and the subsequent simulation and verification of the generated code, undefined signals recurrently occur which are characterized in that they cannot be uniquely assigned one of the two binary states (“0” or “1”). An advantage of the solution according to the invention is to be seen in the fact that the generated code is considerably more robust with regard to the processing of undefined signals, in particular during the simulation. In a further, very advantageous embodiment of the invention it is provided that the code generated according to the invention is mapped to memory cells so that the input signals and their respective combinations or, as the case may be, assignments are mapped to the addresses of the memory cell and that the output signals are assigned the contents of the respective address of the memory cell. The memory cells can be e.g. RAM cells of an FPGA or of some other programmable chip or ROM cells. An important advantage of this embodiment is to be seen in that the total execution time can be reduced even in the case of complex circuits comprising a plurality of gates, since the RAM cells have a fixed (and also fast) timing behavior. Furthermore it is possible that the RAM cells can map input signal functions which map 12 or more inputs.

[0019]As a result of the above described mapping of the code to RAM cells by means of the synthesis tool, a further feature of this embodiment is to be seen in that a state machine of this type can also be modified dynamically. In other words, the state machine can also be modified without the need to reconfigure or at least partially reconfigure the FPGA. This can prove very advantageous, in particular in the case of a rapid switching of algorithms.

Problems solved by technology

Secondly, it is possible to use a tool, specifically a graphical model with predefined syntax, which simplifies and automates the description of state machines and in addition results in a unique and syntactically error-free code.

If the first of the aforementioned possibilities is chosen and the VHDL code is programmed manually, this is more problematical, more complicated and time-consuming, and less convenient, and has the disadvantages that the VHDL code may not be unique and possibly not free of syntactical errors.

A problem with the previous code generation based on a graphical input mode is to be seen in the fact that the generated code exhibits a lack of efficiency, since often unnecessarily many gates or, as the case may be, cells are generated and the clock frequency is low.

The existing prior art solutions therefore reveal themselves as deficient.

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