Electronic device and method for fabricating the same

Abstract

The electronic device comprises a first substrate 10 with an electric circuit element formed in a predetermined region of one primary surface, a second substrate 12 formed, opposed to said one primary surface of the first substrate 10, sealing portions 26, 40 formed between the first substrate 10 and the second substrate 12, enclosing the predetermined region of the first substrate 10, and an adhesion layer 42 formed on the side surfaces of the sealing parts 26, 40. The adhesion layer is formed on the side surfaces of the first sealing structure 26 on the side of the first substrate 10 and the second sealing structure 40 on the side of the second substrate 12, whereby when the first sealing structure 26 and the second sealing structure 40 are bonded to each other, the adhesion between the first sealing structure 26 and the second sealing structure 40 can be sufficiently ensured.

Description

CROSS-REFERENCE TO RELATED APPLICATION [0001] This application is based upon and claims priority of Japanese Patent Application No. 2005-22694, filed on Jan. 31, 2005, the contents being incorporated herein by reference. BACKGROUND OF THE INVENTION [0002] The present invention relates to an electronic device and a method for fabricating the electronic device, more specifically, an electronic device having electronic circuit elements hermetic sealed and a method for fabricating the electronic device. [0003] As electronic circuit elements are increasingly highly integrated by the progress of the recent micronization technology, drastic increase of the processing speed and the cost reduction have been realized. [0004] Semiconductor devices for industrial apparatuses, and cars are considered to be used in severe environments, as of high temperature, high humidity, etc. The semiconductor chips must be sealed in a package having high sealing performance. [0005] SAW (Surface Acoustic Wave)...

AI Technical Summary

Benefits of technology

[0022] An object of the present invention is to provide an electronic device which can seal electronic circuit elements with high sealing performance without much cost increase and larger-sizing, and a method for fabricating the electronic device.

[0026] According to the present invention, the adhesion layer is formed on the side surfaces of the first sealing structure on the first substrate and the second sealing structure on the second substrate, whereby when the first sealing structure and the second sealing structure are bonded to each other, the adhesion between the first sealing structure and the second sealing structure can be sufficiently ensured.

[0027] Thus, according to the present invention, the first sealing structure on the first substrate and the second sealing structure on the second substrate can be bonded to each other without failure. Furthermore, the first sealing structure on the first substrate and the second sealing structure on the second substrate are bonded by intermetallic solid phase diffusion bonding, whereby very high sealing performance can be ensured. Furthermore, chips may not be sealed in large sealing packages, which can contribute to small-sizing. Wafer level-chip size package (WL-CSP) can be used, and in addition, it is not necessary to seal chips in expensive sealing packages, which can decrease the fabrication cost. Accordingly, the present invention can provide, without large cost increase and larger-sizing, electronic devices which can ensure high sealing performance.

[0028] According to the present invention, the first electrode on the first substrate and the second electrode on the second substrate can be integrated with each other by intermetallic solid phase diffusion bonding without being melted, which prevents the first electrode and the second electrode from being melted to spread horizontally when the first electrode and the second electrode are bonded to each other.

[0029] Thus, according to the present invention, even when the first electrode and the second electrode are formed at a small pitch, the short-circuit between the neighboring first electrode and second electrode can be prevented. Accordingly, the present invention can provide electronic device of very high reliability.

[0031] Accordingly, sufficient contacdt areas can be obtained beween the first sealing structure and the second sealing structure and between the first electrode and the second electrode. Thus, according to the present invention, the bonding can be provided by very good intermetallic solid phase diffusion bonding without applying high-pressure from the outside or setting high thermal processing temperatures.

Problems solved by technology

However, in the conventional methods, the metal cover, the package of ceramics or others are expensive, which increases the cost.

The cover and the package itself are relatively large, which might be a barrier to smaller-sizing the electronic device.

Furthermore, the above-described patent references have the following problem.

However, this structure has a problem that stresses are applied to the SAW chips due to high bonding temperatures of the intermetallic compound.

However, this structure has a problem that the barrier bumps (of solder, gold or others) are melted to be bonded, and the integrated circuit chips are susceptible to stresses of the thermal expansion coefficient.

It is difficult to control the thickness of the barrier bumps.

However, this structure has a problem that the inside chips are exposed to the high glass melting temperatures and are damaged.

It is also a problem that to ensure sufficient seal strength, a thickness which is several times a thickness required for the sealing with a metal cover or others is required.

This technique has a problem that the structure is complicated, and the material of the metal spring, etc. is expensive.

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