Method and apparatus for directory-based coherence with distributed directory management utilizing prefetch caches

Abstract

The present invention provides for a type of parallel processing architecture in which a plurality of processors has access to a shared memory hierarchy level. A memory hierarchy level has a coherence directory and associated directory data with a plurality of cachelines each associated with different data. Prefetch caches are interconnected to processor memory and a plurality of processor elements, each element interconnected to different buffers. Cache lines are requested from memory, and the requests, responses, and detections therein are available for particular access modes, therein providing additional coherence of the data. Processing of said directory data is performed by processing elements. In one embodiment, the system comprises an integrated prefetch cache.

Description

CROSS-REFERENCED APPLICATIONS [0001] This application relates to co-pending U.S. patent application entitled “A Method and Apparatus for Directory-Based Coherence with Distributed Directory Management” (Docket No. AUS920030719US1), filed concurrently herewith.TECHNICAL FIELD [0002] The present invention relates generally to the field of multiprocessor computer systems and, more particularly, coherence implementation in a multiprocessor system. BACKGROUND [0003] A shared memory processor (SMP) consists of processor nodes and memories combined into a scalable configuration. Each node has one or more processors and its local memory. Optionally, each node has a cache and a cache controller for accessing main memory efficiently and enforcing consistency. However, a shared memory SMP differs from a network of workstations because all nodes share the same global address space. Hence, software techniques for mapping the global address space into local addresses are typically not needed in a...

AI Technical Summary

Problems solved by technology

If one processor updates the data in its cache without informing the other processor in some manner, an inconsistency results, and it becomes possible that the other processor will use a stale data value.

There are at least two major factors affecting cache mechanisms: performance and implementation cost.

If the time to access main memory is too slow, performance degrades significantly, and potential parallelism is lost.

Implementation cost is also an issue because the performance must be obtained at a reasonable cost.

Implementation costs occur by adding additional coherence hardware, or by programming consistency enforcing compilers.

In addition to these two major factors, there are four primary issues to consider when designing a cache coherence mechanism.

Fourth is caches block sizes, which are the size of a line in the cache, and how it further affects system performance.

However, while CDRAMs can have extremely high bandwidth on dedicated busses, they often have no logic execution ability, increasing the coherency problem.

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