Semiconductor device having porous structure

Abstract

A semiconductor device having a hollow structure includes: a substrate on which a wiring layer is formed; a low-dielectric layer with a porosity of 6% to 25% having vias and trenches and having voids between adjacent vias; and a contact layer of copper with which the vias and trenches are filled. The contact layer is in contact with the wiring layer and an upper surface of the contact layer is exposed from the dielectric layer.

Description

[0001] This is a divisional application of U.S. patent application Ser. No. 10 / 693,200, filed Oct. 24, 2003, which claims the benefit of U.S. Provisional Application No. 60 / 422,956, field Oct. 31, 2002, the disclosure of which is incorporated herein by reference in their entirety.BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] This invention relates to a technology of manufacturing semiconductor devices having a porous structure and voids (air-gaps), and particularly relates to a technology that involve selectively etching a sacrificial film. [0004] 2. Description of the Related Art [0005] In recent years, semiconductor devices have become faster and more highly integrated and resistance-capacitance (RC) coupling delays have become a large factor in signal processing time. RC delays can be decreased by reducing wiring capacitance. One way to do this is to use low dielectric constant materials such as fluorine-doped SiO2, porous SiO2, an organic film or a porous f...

AI Technical Summary

Benefits of technology

[0010] In an aspect, an embodiment of the present invention provides a method for manufacturing a semiconductor device, comprising the steps of: (i) depositing a sacrificial layer on a substrate having a circuit formed thereon; (ii) etching the sacrificial layer except for a portion where air gaps are to be formed; (iii) depositing a low-dielectric layer over the substrate until the portion for air gaps is entirely enclosed in the low-dielectric layer; (iv) etching the low-dielectric layer to form via holes (“vias”) and trenches therethrough; (v) prior or subsequent to step (iv), removing the portion for air gaps of the sacrificial layer; and (vi) depositing copper in the vias and trenches which are filled with the copper contacting a surface of the substrate. By the above method, an ELK film having excellent mechanical properties and excellent applicability to the Dual Damascene process can effectively and easily be obtained. In the above, an etch stop layer can be used before depositing a low-k film. The purpose of the etch stop layer may have two folds; as a mechanical support and as a reference etch stop layer for stopping etch.

Problems solved by technology

However, this approach has disadvantages: The deposited dielectric layer has a very high porosity (e.g., >30%) with bimodal or trimodal pores with pore sizes ranging from 2 nm to 9 nm or higher.

Thus, mechanical properties of the layer are very low, particularly hardness and cohesive strength.

Also, because of large pores, new and costly processes may be required for the Dual Damascene integration with copper.

This processes may result in poor yields and also pose very high challenge for successful integration with copper.

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