Method for producing a multichip module and multichip module

Abstract

A method for producing a multi-chip module having application of at least one contact elevation onto a substrate, application and patterning of a rewiring device onto the substrate and the at least one contact elevation with provision of a contact device on the at least one contact elevation, application of a semiconductor chip onto the substrate with electrical contact-connection of the rewiring device; application of an encapsulating device that is not electrically conductive onto the semiconductor chip, the substrate, the rewiring device and the at least one contact elevation, the contact device on the at least one contact elevation at least touching a first surface of the encapsulating device; and repetition at least once of at least the first two steps, the first surface of the encapsulating device serving as a substrate and the correspondingly produced rewiring device making electrical contact with the contact device of the at least one contact elevation of the underlying plane.

Description

CLAIM FOR PRIORITY [0001] This application claims the benefit of priority to German Application No. 103 45 391.1, which was filed in the German language on Sep. 30, 2003, the contents of which are hereby incorporated by reference. [0002] 1. Technical Field of the Invention [0003] The present invention relates to a method for producing a multichip module and a corresponding multichip module, and in particular, to a method for producing a multichip system in a package. [0004] 2. Background of the Invention [0005] In order to be able to provide complete semiconductor system solutions, it is necessary to be able to integrate different functional units within a component. For such integration, it is possible on the one hand to choose an SoC approach (system on chip) or on the other hand an SiP approach (system in a package). SiP solutions afford the advantage that, within a package, separate chips can in each case be individually optimized, tested and produced cost-effectively as functio...

AI Technical Summary

Benefits of technology

[0013] In another embodiment of the invention, a multiplicity of chips in a chip stack can advantageously be connected to one another in a simple and cost-effective manner. The use of cost-intensive rewiring substrates or disadvantageous bonding wires can thus be avoided. Following the production method according to the invention, a high degree of parallelism is made possible in the production process since, by way of example, 12 inch substrates or rectangular substrates or else a reel-to-reel method can be used. Complex metallization and filling of contact holes is not necessary, just as little as vertical patterning after separation of the chip stack along chip edges.

Problems solved by technology

What is problematic in the case of SiP solutions is that the individual chips within the package, preferably within a chip stack, have to be electrically conductively connected together among one another.

Based on the high inductance and capacitance of the bonding wire, many connecting points and a lack of impedance matching.

Such an arrangement gives rise to long signal paths, however, which likewise result in poor electrical properties at high frequencies.

What is more, such a known arrangement is associated with high substrate costs.

The complex processing associated with high costs is disadvantageous in this case.

This gives rise to the disadvantages that free areas have to be provided on the chip for through-plating, which necessitates an enlargement of the chip area.

Moreover, the processing is complex and associated with high costs in this case as well.

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