Clock distribution networks and conductive lines in semiconductor integrated circuits

Abstract

A clock distribution network (110) is formed on a semiconductor interposer (320) which is a semiconductor integrated circuit. An input terminal (120) of the clock distribution network is formed on one side of the interposer, and output terminals (130) of the clock distribution network are formed on the opposite side of the interposer. The interposer has a through hole (360), and the clock distribution network includes a conductive feature going through the through hole. The side of the interposer which has the output terminals (130) is bonded to a second integrated circuit (310) containing circuitry clocked by the clock distribution network. The other side of the interposer is bonded to a third integrated circuit or a wiring substrate (330). The interposer contains a ground structure, or ground structures (390, 510), that shield circuitry from the clock distribution network. Conductive lines (150) in an integrated circuit are formed in trenches (610) in a semiconductor substrate.

Description

BACKGROUND OF THE INVENTION [0001] The present invention relates to placement of clock distribution networks and fabrication of conductive lines in semiconductor integrated circuit structures. [0002]FIG. 1 shows a tree-like clock distribution network 110 designed to distribute a clock signal with a minimum clock skew in an integrated circuit. The clock signal is received at a terminal 120 and distributed to terminals 130 at the leaves of tree 110. Terminals 130 are connected to inputs of circuit blocks 140 such as registers, flip flops, latches, logic gates, etc. The network tree is provided by conductive lines 150. The wires 150 that connect the tree nodes of each given tree level to the tree nodes of any given adjacent level have the same dimensions. Buffers (amplifiers) 160 are located at selected points in the tree to amplify the clock signal. In order to minimize the clock skew, each clock path from terminal 120 to a terminal 130 has the same dimensions, and the respective buff...

AI Technical Summary

Benefits of technology

[0010] In some embodiments of the invention, some or all of the contact pads 323, and at least a contact pad that serves as the input terminal of the clock distribution network, are moved to the bottom of die 320. The bottom contact pads 323 are connected to circuitry at the top of the die by means of conductive features forming large angles (e.g. 90°) with the top and bottom surfaces of die 310. Since large portions of lines 150 extend along the top surface of die 310, the electromagnetic interference and the parasitic capacitance can be reduced.

[0015] In some embodiments, the clock distribution lines 150 (FIGS. 1, 2) are formed in trenches etched in a semiconductor substrate. The RC value of lines 150 can be lowered by making the trenches deeper, without increasing the lateral area occupied by the RC lines. Also, the RC value, and hence the clock skew, become more controllable.

Problems solved by technology

A perfect placement of a clock distribution network on a semiconductor die can be difficult due to the presence of other circuitry.

As a result, it is difficult to control the impedance of lines 150 and therefore the clock propagation speed.

Further, the ground plane or grid consumes valuable area, increases the cost and complexity of the integrated circuit, and sometimes does not completely eliminate the electromagnetic interference problem because the position of the ground plane or grid can be restricted to allow the same metal layer to be used for other circuit elements.

The small angles when combined with small spacing between a line 324 or 326 and a line 150 may lead to significant electromagnetic interference and parasitic capacitance.

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