Insulated gate field effect transistor and manufacturing method thereof

Abstract

A separation hole is provided in the center of the gate electrode. Accordingly, it is possible to suppress a drastic increase in feedback capacitance Crss in the case where drain-source voltage VDS is decreased and the width of the depletion layer is narrowed. Thus, high-frequency switching characteristics are improved. Moreover, n type impurities are implanted from the separation hole to form an n type impurity region between channel regions. Since a resistance in a portion below the gate electrode can be reduced, an on-resistance can be reduced. The n type impurity region can be formed in a self-aligning manner.

Description

technical field [0001] The invention relates to an insulated gate field effect transistor and a manufacturing method thereof, in particular to an insulated gate field effect transistor capable of reducing feedback capacitance and a manufacturing method thereof. Background technique [0002] Referring to FIG. 16, a conventional insulated gate field effect transistor will be described taking an n-channel MOSFET as an example. [0003] As shown in FIG. 16, an n-type semiconductor layer is stacked on an n+-type silicon semiconductor substrate 21, and a drain region 22 is provided. A plurality of p-type channel regions 24 are provided on the surface of the drain region 22 . A gate electrode 33 is provided on the surface of the n − -type semiconductor layer 22 between adjacent channel regions 24 via a gate insulating film 31 . The periphery of the gate collector 33 is covered with an interlayer insulating film 36 . In addition, an n+ type source region 35 is provided on the sur...

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Problems solved by technology

[0015] However, since the integral value of the region x is determined by the drain-source voltage VDS applied to the MOSFET in the on state as shown in Fig. 17(B), there is a limit to improving the high-frequency switching characteristics.

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