High-precision number cosine converting circuit without multiplier and its conversion

A cosine transform, high-precision technology, applied in the direction of digital video signal modification, instruments, electrical components, etc., can solve the problems of low calculation accuracy, increased calculation steps, increased calculation delay, etc., to achieve high calculation accuracy, high Parallelism and coherence, the effect of simple hardware circuits

Active Publication Date: 2006-11-01
XIAMEN UNISOC TECH CO LTD
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0019] However, the calculation accuracy is not high when using several serial shifts and addition and subtraction to replace a multiplication scheme
If the IEEE Std 1180-1990 standard is to be met, the addition and subtraction required may be greater than the multiplication saved
In addition, the serial shift and addition and subtraction increase the calculation steps, resulting in increased calculation delay, which is not conducive to the use of hardware to realize high-speed DCT circuits

Method used

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  • High-precision number cosine converting circuit without multiplier and its conversion
  • High-precision number cosine converting circuit without multiplier and its conversion
  • High-precision number cosine converting circuit without multiplier and its conversion

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Embodiment Construction

[0058] The present invention adopts another train of thought to realize the interleaved multiplication-addition unit circuit in Chen scheme, has realized a kind of high-precision " non-multiplier DCT conversion circuit ", and now describes in detail as follows:

[0059] Such as Figure 5 As shown, if the multiplication factors a and b of the core computing units of the Chen scheme and the Loeffler scheme are divided by s, the output is also divided by s, so the output needs to be multiplied by s to get the correct result. The core idea of ​​the present invention is to select appropriate A and B values ​​by changing the value of s, so that A≈a / s and B≈b / s, where A and B are natural numbers, and the number of digits required for binary expression is as few as possible , and contains the least number of "1" or "-1". For example, A and B are limited to natural numbers less than or equal to 24, and only contain no more than two "1" or "-1", then multiplying A or B can be replaced ...

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Abstract

The invention is a high rigorous number cosine commutation and quantified method without multiplier. Two shifters and one plus-subtracter complete the number cosine commutation with the scale coefficient-s, instead of one multiplier. The commutation export result multiplies with L in order to get DCT commutation result, and s divides quantified coefficient to get the L. The hardware circuit can avoid using the energy-consuming multiplier by selecting given number. It is a kind of no multiplier DCT commutation with massive parallel and consistency. The hardware account unit can be used for many times so the hardware circuit is very simple. The DCT and IDCT can be realized though a hardware circuit and get high account precision.

Description

technical field [0001] The invention relates to a digital cosine transformation circuit without a multiplier and a transformation method thereof. Background technique [0002] In the encoding process of most static image compression standards (such as JPEG) and dynamic image compression standards (such as MPEG1, MPEG2, MPEG4, H263, etc.), the original image data (or motion The estimated image data) is transformed from the time domain to the frequency domain, and then the frequency domain signal (that is, the result of the DCT) is quantized by a quantizer, and finally the quantized frequency domain signal is compressed. During this process, the quantizer completes the operation of dividing the frequency domain signal by a specific quantization coefficient, usually by multiplying the frequency domain signal by the reciprocal of the quantization coefficient. [0003] The decoding process is as follows: first decompress the compressed code stream to obtain the quantized frequen...

Claims

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Application Information

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IPC IPC(8): G06T9/00H04N1/41H04N19/124H04N19/42H04N19/625
Inventor 林豪
Owner XIAMEN UNISOC TECH CO LTD
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