Semiconductor memory device and refresh control method

Abstract

Disclosed is a semiconductor-memory device comprising a selector for performing switching control such that in the standby state the refresh operation is performed responsive to an external-refresh-execution command supplied from outside the semiconductor-memory device, while in the active state, the refresh operation is performed, not under the control from outside the semiconductor-memory device, but under the control from a built-in timer.

Description

technical field [0001] The present invention relates to a semiconductor storage device, and more particularly to a semiconductor storage device requiring refresh for data retention and a refresh control method thereof. Background technique [0002] A dynamic semiconductor memory device (DRAM), which consists of one transistor and one capacitor per unit, occupies a small area. However, it records information by accumulating data in the capacitor, so due to leakage current, the accumulated The charge will decrease over time. Therefore, it is necessary to perform a refresh operation of reading stored information in a memory cell to a sense amplifier and writing the read data from the sense amplifier to the memory cell before the stored information is lost. On the other hand, in a static type semiconductor memory device (SRAM), the memory cell is composed of flip-flops and does not require a refresh operation. However, one memory cell is composed of, for example, four transisto...

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Problems solved by technology

On the other hand, in a static type semiconductor memory device (SRAM), the memory cell is composed of flip-flops and does not require a refresh operation. However, one memory cell is composed of, for example, four transistors and two load elements, so the memory cell occupies The area is larger than that of DRAM. As a large-capacitance memory, when SRAM is used, the chip area will increase

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