Nonvolatile semiconductor memory device and read method

Abstract

This device comprises a memory cell selecting circuit 17 for selecting the memory cell from the memory cell array 15 in units of row, column or memory cell, a read voltage application circuit 22a for applying a read voltage to the variable resistor element of the selected memory cell selected by the memory cell selecting circuit 17, and a read circuit 23 for detecting the amount of the read current flowing in accordance with the resistance value of the variable resistor element with respect to the memory cell to be read of the selected memory cells and reading the information stored in the memory cell to be read. The read voltage application circuit 22a applies a dummy read voltage having reversed polarity from the read voltage to the variable resistor element of the selected memory cell.

Description

technical field [0001] The present invention relates to a semiconductor memory device having a memory cell array in which a plurality of memory cells including variable resistance elements which store information using changes in resistance are arranged in a row direction and a column direction respectively, and more specifically relates to preventing and A technique for suppressing the deterioration of the quality of stored data accompanying the read operation of a memory cell array. Background technique [0002] In recent years, FeRAM (Ferroelectric RAM: ferroelectric RAM), MRAM (Magnetic RAM: magnetic Resistor RAM) and OUM (Ovonic Unified Memory: phase-change memory) and other device structures have launched fierce development competition in terms of high performance, high reliability, low cost, and process matching. [0003] In addition, for these prior technologies, Shangquing Liu and Alex Ignatiev of the University of Houston in the United States...

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Problems solved by technology

Furthermore, when the same memory cell is repeatedly read and the read operation is performed, in the worst case, there is a possibility that the stored data will completely disappear and cannot be read.

[0024] Furthermore, in a memory cell array composed of 1R type memory cells, since the read voltage is also applied to the selected memory cells other than the read target memory cells sharing the word line or bit line with the read target memory cells, the above-mentioned read disturbance phenomenon more obvious

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