Method for generating gate controlled clock unit according to standard cell base element directly

Abstract

This invention relates to integration circuit technique field direct standard unit database parts clock units generating method, which comprises the following steps: unit structure defining, structure building, layout distributing, RC parameter extracting, time series database files; physical files generating and testing module, wherein, the layout and lead leg is set on the adjacent metal layer channel to make the output direction on level and crossed layers to realize the lead leg use and to prevent shielding layer on the door controlled clock unit.

Description

technical field [0001] The invention relates to a method in the technical field of integrated circuits, in particular to a method for directly generating a gate clock unit according to a standard cell library device. Background technique [0002] The gated clock unit is currently a popular low-power design method in the SOC field, that is, when some large modules are not working, the clock signal inside the module is turned off, thereby reducing the dynamic power consumption inside the module and realizing low power consumption of the chip. consumption design. The use of gate-controlled clocks in ordinary integrated circuit processes is generally divided into the following categories: entrust OEMs to design through production lines or directly purchase from OEMs, that is, use real physical devices to build and test, and thus obtain relevant information. Timing and physical data. The test results of this method are more accurate, and the integrated circuit design department...

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Problems solved by technology

The test results of this method are more accurate, and the integrated circuit design department is more convenient to use, but the disadvantage is that the cost is high; using RTL language to build directly, the advantage of this method is that the integrated circuit design department is easier to implement, and the front-end design and test verification are also very convenient , but it also has certain defects: if the back-end layout and routing are set to automatic layout, the physical distance between the devices cannot be controlled, the connection of the devices is very loose, the real binding of the structure cannot be realized, and it is easy to cause disadvantages in the timing slot The impact of custom circuit design, but the flexibility of chip design cannot be realized. Once the process is changed or the structure is adjusted, the circuit and its size, restriction rules, etc. need to be re-formulated.

However, because this method cannot completely bind the components of the gate control unit in physical locations, its impact on the overall delay and area of ​​the circuit is not fixed. At the same time, because the gate control clock unit cannot be instantiated in the front-end design, It will cause some inconvenience to the overall design verification of the chip

[0004] It can be seen that the traditional method of building or using the gated clock has imposed various restrictions on the integrated circuit design department in terms of economy and efficiency. Therefore, it is very necessary to find a reasonable and simple Direct method of generating clock gating

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