Frequency synthesizer of using all-digit frequency detector and analogue phase detector

Abstract

A frequency synthesizer suitable for integration in a low voltage digital CMOS process controls a VCO using a dual loop structure including an analog loop and a digital loop. The digital loop includes an all digital frequency detector, which controls the center frequency of the VCO. The analog loop includes an analog phase detector and charge pump, which add phase coherence to the frequency controlled loop, thus eliminating any static frequency error. In effect, the analog loop reduces the noise of the digital logic and VCO, and the digital control provides frequency holdover and very low bandwidth. The bandwidth of the digital loop is made much smaller than the bandwidth of analog loop, and is preferably 200 times smaller. This gross parametric difference is used in the design of the VCO to allow two separate control inputs, one from the analog loop and one from the digital loop, with both inputs functioning relatively independently of each other.

Description

technical field [0001] The present invention relates generally to the field of integrated frequency synthesizers and oscillators. In particular, the present invention is in the field of implementing variable voltage oscillators using low voltage digital CMOS processes. Background technique [0002] In modern communication systems, high-speed phase-locked loops are used for a variety of purposes, including frequency synthesis operations such as clock generation, data recovery, and retiming. This frequency synthesizer is usually an analog circuit, but in order to reduce costs, the industry tends to use a low-voltage digital CMOS process to implement this circuit. [0003] Frequency synthesizers are usually voltage controlled, so when implementing a frequency synthesizer in a low-voltage digital CMOS process, you encounter signal headroom and scalability issues. Despite these issues, the use of advanced sub-micron digital CMOS processes for implementing analog clock generatio...

AI Technical Summary

Problems solved by technology

[0005] Although a corollary of this trend is the availability of complex digital functions in the smallest area possible, integrating complex high-speed digital functions near low-headroom, high-gain analog clock components is known to result in spurious frequencies and higher jitter content

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