Technique for repairing salient point and memory by using laser

Abstract

First, the first dielectric layer is formed on the salient welding spot of the semiconductor chip. Next, the first dielectric layer is etched in order to form a contact hole and expose a part of the salient welding spot. Then, the second dielectric layer is formed on the surface outside the contact hole in the semiconductor chip. A metallization process is carried out for the bottom of the salient point in order to form a metal layer on the surface of the contact hole, and form a solder salient point on the metal layer. Finally, the procedure of laser-patching memory is completed.

Description

technical field [0001] The invention relates to a process of laser repairing (Laser Repair) of a memory after solder bumps are completed. Background technique [0002] In today's packaging technology, high-efficiency electronic components usually use solder balls or solder bumps to achieve the purpose of electrical and mechanical connection with each other. For example, an ultra large scale integration (ULSI) can use solder balls or solder bumps to form electrical connections with a circuit board or other second stage packaging substrate. Connection, this connection technology is called flip-chip packaging (Flip-chippackaging, FC). [0003] Please refer to Figure 1 to Figure 4 , Figure 1 to Figure 4 It is a schematic diagram of a conventional memory laser repair process on a semiconductor chip 10 . Such as figure 1 As shown, the semiconductor chip 10 includes a substrate 12 on which an integrated circuit region (not shown) is formed, and the int...

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Problems solved by technology

[0006] Since the prior art is to perform the circuit test and the laser repair process first, it may affect the subsequent formation of the second dielectric layer 22 and the metal layer 24

First of all, the circuit testing procedure directly connects the probe pins to the bump pads 14, so a serious probing mark may be formed on the bump pads 14 surface, and subsequently formed on the bump pads 14 surface The step coverage of the metal layer 24 is very poor, which will cause the loss or weakening of the metal layer 24's adhesion and diffusion barrier function, thereby affecting product reliability.

In addition, when the metal interconnect (interconnect) system utilizes copper process technology and low dielectric constant material as the insulating layer between the metals, the circuit test procedure directly performed on the bump pad 14 may face failure due to excessive test force. Caused bare copper or insulation cracks and other problems

At the same time, the oxidation of the detection marks on the copper gasket after needle testing is also a difficult challenge.

[0007] Secondly, since the laser repair process carried out after completing the circuit test program will cut off part of the fuse structure 16, a plurality of trenches (trench) 27 with a larger aspect ratio (aspect ratio) are formed on the surface of the semiconductor chip 10. , which in turn may produce voids in the second dielectric layer 22 filled in later, affecting product reliability

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