Phase conversion bimodulux prescaler circuit with device for reducing power consumption

Abstract

The dual-modulus prescaler circuit for a frequency includes several dividers-by-two of the asynchronous type, connected in series, a phase selector unit (11) inserted between two of the dividers-by-two (11, 12a) and a control unit for supplying first control signals(S0, S1, S2, C1, C2) to the selector unit as a function of a selected mode. Said control unit receives four signals phase shifted by 90 DEG with respect to each other from a first master-slave divider and supplies a selected one of the four phase shifted signals. The selector unit includes a first amplifying branch (21) receiving two first phase shifted signals, a second amplifying branch (22) receiving two second phase shifted signals, and a selection element (23) connected to each branch. The first control signals (S0, S1, S2) are supplied to the first and second branches, and to the selection element for selecting one of the four phase shifted signals (F2) at one output in a determined division period. The selector unit (11) includes switching means (24, 26) controlled by second control signals for disconnecting the electric power supply to one of the selection branches when the other branch is selected to supply one of the four phase shifted signals at the output of the selector unit.

Description

field of invention [0001] The present invention relates to a phase shifting dual analog-to-digital prescaler circuit having means for reducing power consumption. The dual modulus prescaler or divider counter circuit forms part of a frequency synthesizer. The circuit divides at least the high-frequency signal by a factor N in a first selection mode and by a factor N+M in a second selection mode. It consists of several asynchronous divide-by-twos connected in series. One of these divide-by-twos is a master-slave type that accepts two input signals that are out of phase and provides four signals that are 90° out of phase with each other. The circuit also includes a phase selector unit inserted between the two dividers for receiving the four phase-shifted signals from the first master-slave divider and providing the four phase-shifted signals selected by the second divider. One of the phase signals. The two selection branches of the selector unit each receive two of the four p...

AI Technical Summary

Problems solved by technology

[0017] Another disadvantage of the solution disclosed in the paper by Messrs.Craninckx and Steyaert is that the amplifier of the selector unit consumes a large amount of current in order to amplify relatively high frequency signals

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