Electronic package and fabrication method thereof

Abstract

The invention relates to an electronic package and a manufacturing method thereof, comprising the steps of forming at least two heat dissipation materials on an electronic component, and combining a heat dissipation piece with the electronic component through the at least two heat dissipation materials, and one of the at least two heat dissipation materials is liquid metal, so that the heat dissipation effect of a hot spot area of the electronic component is improved.

Description

technical field [0001] The present invention relates to a package structure, in particular to an electronic package with a heat sink and a manufacturing method thereof. Background technique [0002] With the improvement of the function and processing speed of electronic products, the semiconductor chip as the core component of the electronic product needs to have higher density electronic components (Electronic Components) and electronic circuits (Electronic Circuits), so the semiconductor chip will change with the time of operation. produces a greater amount of thermal energy. In addition, because the traditional encapsulation compound covering the semiconductor chip is a thermal conductivity of only 0.8 (unit W.m -1 .k -1 ) of the poor heat transfer material (that is, the heat dissipation efficiency is not good), so if the heat generated by the semiconductor chip cannot be effectively dissipated, it will cause damage to the semiconductor chip and product reliability prob...

AI Technical Summary

Problems solved by technology

[0006] However, in the existing semiconductor package 1, only a single heat dissipating glue is used as the TIM layer 12, and its thermal conductivity is poor, resulting in limited heat dissipation, especially in the hot spot (hot spot) area of ​​the semiconductor chip 11 (such as the non The middle or corner of the active surface 11b) has poor heat dissipation, so it is difficult to meet the high heat dissipation requirements of the semiconductor package 1

[0007] In addition, when the thickness of the semiconductor package 1 is thinned and the area is increased, the deformation (that is, the degree of warping) between the heat sink 13 and the TIM layer 12 due to the difference in coefficient of thermal expansion (CTE Mismatch) is more serious. Obviously, when the amount of deformation is too large, delamination is likely to occur between the top sheet 130 of the heat sink 13 and the TIM layer 12 (or with the semiconductor chip 11), which not only causes the heat conduction effect to decrease, but also causes the semiconductor chip 11 or primer 111 cracks, resulting in problems such as poor reliability and low process yield of the semiconductor package 1

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