Semiconductor memory cell structure, semiconductor memory and preparation method and application thereof

Abstract

The invention relates to a semiconductor memory cell structure, a semiconductor memory and a preparation method and application thereof. The semiconductor memory cell structure comprises a substrate, a first transistor layer, an isolation layer and a second transistor layer, the first transistor layer comprises a first stacking structure formed by stacking a first source electrode, a first channel and a first drain electrode from bottom to top, and a first grid electrode located on the side wall of the first stacking structure; the second transistor layer comprises a second stacking structure and a second grid electrode, the second stacking structure is formed by stacking a second drain electrode, a second channel and a second source electrode from bottom to top, the second grid electrode is located on the side wall of the second stacking structure, and at least one part of the side wall of the second drain electrode is in direct contact with the first grid electrode. The DRAM has the advantages of vertical stacking integration, high integration level, low electric leakage, short refresh time and the like, and has remarkable advantages compared with an existing 2T0C type DRAM.

Description

technical field [0001] The invention relates to the field of semiconductor memory, in particular to a structure of a semiconductor memory unit, a semiconductor memory and a preparation method and application thereof. Background technique [0002] A higher degree of integration of semiconductor devices may be desirable to satisfy consumer demand for superior performance and low price. For semiconductor devices, an increase in the degree of integration is particularly desirable since their degree of integration can be an important factor in determining product prices. For two-dimensional or planar semiconductor devices, since their degree of integration is mainly determined by the area occupied by a unit memory cell, the degree of integration is greatly affected by the level of fine pattern formation technology. However, extremely expensive process equipment for increasing pattern fineness sets practical limits to increasing the integration of two-dimensional or planar semico...

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Problems solved by technology

3D integration is a breakthrough for DRAM scaling, but the need for storage capacitors limits the scalability of 3D DRAM cells

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