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Memory self-checking device and method

A self-checking device and memory technology, applied in static memory, instruments, etc., to achieve the effects of simple method, improved detection efficiency, and reduced logic resource consumption

Pending Publication Date: 2022-04-12
SHANGHAI INTEGRATED CIRCUIT RES & DEV CENT +1
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In the normal use stage, there is no external tester, and the product also needs an internal test circuit to check its own faults

Method used

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  • Memory self-checking device and method
  • Memory self-checking device and method
  • Memory self-checking device and method

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Embodiment Construction

[0047] In order to make the purpose, technical solutions and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the present invention. Obviously, the described embodiments are part of the present invention Examples, not all examples. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present invention. Unless otherwise defined, the technical terms or scientific terms used herein shall have the usual meanings understood by those skilled in the art to which the present invention belongs. As used herein, "comprising" and similar words mean that the elements or items appearing before the word include the elements or items listed after the word and their equivalents, without excluding other el...

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Abstract

The invention provides a memory self-checking device and method, and the device comprises a control module which is used for generating a target input signal according to an input starting enable signal, and generating a first selection control signal and a second selection control signal respectively; the first selection module is used for receiving a first selection control signal and a target input signal and outputting a first selection output signal to the to-be-tested storage module; the second selection module is used for receiving a second selection control signal and the first storage output signal, performing data selection on the initial signal and the first storage output signal and generating a second selection output signal; the receiving module is used for receiving the first storage output signal and the detection control signal; wherein the receiving module detects the first storage output signal according to the detection control signal and obtains a detection result, and the control module outputs a target output signal according to the detection result. According to the invention, the memory can be effectively checked, the detection efficiency is improved, and the occupation of logic resources is reduced.

Description

technical field [0001] The invention relates to the technical field of semiconductor chips, in particular to a memory self-inspection device and method. Background technique [0002] Defects are likely to be introduced in the chip production process, resulting in product failure. Therefore, semiconductor manufacturers must conduct a comprehensive test on the device before going on the market to eliminate faulty chips and shorten the early failure period of the failure rate curve. In the normal use stage, there is no external tester, and the product also needs internal test circuits to check its own faults. [0003] Complementary Metal Oxide Semiconductor (CMOS) refers to a technology used to manufacture large-scale integrated circuit chips or chips manufactured by this technology, while CMOS image sensor (CMOS image sensor, CIS) chips integrate Multiple blocks of memory, including random access memory (Random Access Memory, RAM) and read-only registers (Read-Only Memory, RO...

Claims

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Application Information

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IPC IPC(8): G11C29/12
Inventor 常钦皓张远
Owner SHANGHAI INTEGRATED CIRCUIT RES & DEV CENT
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