DDR micro-module structure based on TSV wafer reconstruction and multi-layer stacking and preparation technology

Abstract

The invention discloses a DDR micro-module structure based on TSV wafer reconstruction and multi-layer stacking and a preparation technology. The DDR micro-module structure comprises multiple layers of TSV silicon substrates, and every two adjacent layers of TSV silicon substrates are connected through a plurality of micro convex points; a cavity is formed in the upper end face of each layer of TSV silicon substrate, a DDR bare chip is embedded in each cavity, and a PAD of each DDR bare chip faces upwards; and the via hole or BUMP of each layer of TSV silicon substrate is connected with the PAD of the DDR bare chip embedded in the TSV silicon substrate through RDL wiring. The problem that the fan-out area of the bonding wire is increased in an exponential level mode due to increase of the number of stacked layers is effectively solved.

Description

technical field [0001] The invention belongs to the field of multi-component integration of microsystems, and in particular relates to a DDR micromodule structure and preparation process based on TSV wafer reconstruction and multi-layer stacking. Background technique [0002] DDR (Double Data Rate Synchronous Dynamic Random Access Memory) is SDRAM with double data transfer rate, its data transfer speed is twice the system clock frequency, due to the increased speed, its transfer performance is better than traditional SDRAM, widely used In high-performance servers, desktops, notebooks, and other devices. However, subject to the constraints of the tape-out process, such as figure 1 As shown, the external bonding PAD 2 on the DDR bare chip 1 is in the middle position, and this structure is not conducive to the stacking of the DDR bare chip. like figure 2 As shown, the industry generally adopts the RDL (Redistribution Layer, rewiring) method to redistribute the PAD 2 to the ...

AI Technical Summary

Problems solved by technology

This method has the following problems: Due to the limitation of the stack height, the thickness of the gasket 4 used for the stack is generally about 500 μm, and silicon wafers are generally used as the stack gasket

This solution is similar to the above-mentioned solution, but the RDL process is omitted, and it still cannot solve the problem of exponential growth of the fan-out area of ​​the bonding wire 5 and the problem of heat concentration as the number of stacked layers increases.

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