Ultralow-temperature wafer injection platform

Abstract

The invention provides an ultralow-temperature wafer injection platform. The platform at least comprises a front-end wafer conveying module, a loading module, a vacuum conveying module, a vacuum cooling module, a vacuum injection module and a vacuum heating module; the front-end wafer conveying module, the loading module, the vacuum conveying module, the vacuum cooling module, the vacuum injection module and the vacuum heating module are matched with one another to form an integrated body, and the integrated body realizes ultralow-temperature wafer ion implantation; in the vacuum cooling module, a wafer is rapidly cooled through a cooling platform for cooling the wafer and an electrostatic chuck for adsorbing the wafer, so that the wafer is in an ultralow temperature state, and the temperature in the ultralow temperature state is lower than minus 50 DEG C. According to the platform, dynamic annealing in the ion implantation process is effectively inhibited, so that atoms at gap positions cannot return to lattice replacement positions any more, the number of amorphous packages is increased, the range of the amorphous packages is gradually expanded, and finally, the boundaries of all the amorphous packages are connected together to form a complete amorphous layer. According to the platform of the invention, ultralow-temperature ion implantation is realized, and the complete amorphous layer is formed.

Description

technical field [0001] The invention belongs to the field of semiconductor manufacturing and processing, and relates to an ultra-low temperature wafer implantation platform, which is suitable for ion implantation equipment. Background technique [0002] Semiconductor devices have been developing toward miniaturization for a long time. According to Moore's Law, the number of semiconductor devices integrated on a unit area of ​​an integrated circuit chip will double every 18 months, and with the miniaturization of semiconductor devices , Most of the internal structures of semiconductor devices are bound to be scaled down proportionally. At present, the critical dimensions of semiconductor devices have reached the nanometer or deep nanometer level. How to manufacture ultra-shallow junctions and abrupt junctions in semiconductor devices, and how to more completely repair ion implantation end-of-range defects (EOR Damage) in the manufacturing process of semiconductor devices have...

AI Technical Summary

Problems solved by technology

Because of the dynamic annealing phenomenon during normal temperature ion implantation or shallow low temperature ion implantation, normal temperature ion implantation or shallow low temperature ion implantation cannot form the required amorphous layer on the wafer surface well.

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