Six-level assembly line CPU based on RISC-V instruction set

A RISC-V and instruction set technology, applied in concurrent instruction execution, instrumentation, computing, etc., can solve the problem of reduced CPU main frequency and instruction throughput, insufficient division of pipeline stages, low CPU main frequency and throughput, etc. problems, to achieve the effect of increased main frequency, easy control, and reduced execution time

Pending Publication Date: 2022-01-28
NANJING UNIV OF SCI & TECH
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  • Description
  • Claims
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Problems solved by technology

[0004] Although there are many kinds of domestic processors, the division of pipeline stages is not detailed enough, which greatly affects the execution efficiency of the CPU, and the main frequency and instruction throughput of the CPU will be greatly reduced.
Like the more popular domestic Hummingbird E203 processor, there is only a two-stage pipeline structure, which makes the main frequency and throughput of the CPU lower

Method used

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  • Six-level assembly line CPU based on RISC-V instruction set
  • Six-level assembly line CPU based on RISC-V instruction set
  • Six-level assembly line CPU based on RISC-V instruction set

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Embodiment

[0054] The pipeline IF stage circuit is attached figure 1 , consists of an instruction address generating module, an instruction fetching module, and a pc cache module. The working process of the IF level circuit is as follows: in the instruction address generation module, the current pc and the jump pc are added with 4 and then input to the data selector imux1, the pc_sel generation module generates the control signal pc_sel of imux1, and imux1 outputs the next instruction address to the PC counter . In the instruction fetch module, the selector imux2 selects the appropriate address as the input of the ITCM address terminal, and the ITCM outputs instructions according to the input address. The PC buffer can also be used as an inter-segment register between the IF stage and the FD stage, and outputs the PC value of the IF stage to the next stage of the FD stage.

[0055] The pipeline FD level circuit is attached figure 2 , consists of a load_use detection unit, an instruct...

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Abstract

The invention discloses a six-level assembly line CPU based on an RISC-V instruction set. The CPU can realize an RV32I basic instruction set, a multiplication instruction and a CSR read-write instruction, and is provided with an interrupt register to suspend an assembly line; the CPU has the remarkable characteristics that the CPU has six levels of assembly line structures, namely an IF level, an FD level, a CSG level, an EXE level, an MEM level and a WB level, and has a higher dominant frequency; related circuits are designed for solving the risk problems in the assembly line; the data risk is solved by utilizing internal forward pushing, the load_use risk is solved by utilizing an assembly line pause method, and the control risk is solved by utilizing a static prediction method. The CPU has the characteristics of small area, low power consumption and multiple functions, and can be widely applied to the Internet of Things and embedded fields.

Description

technical field [0001] The invention belongs to the field of processor design, in particular to a six-stage pipeline CPU based on a RISC-V instruction set. Background technique [0002] RISC-V ISA is an open instruction set architecture completed by a related team at the University of California, Berkeley. RISC means a reduced instruction set computer, and V means the fifth generation, so this architecture is built based on the principle of reduced instruction set computing. Compared with most instruction sets, the RISC-V instruction set is completely free and open source, allowing anyone to design, manufacture and sell chips and software based on the RISC-V instruction set. Today, microprocessors based on the RISC-V instruction set are widely used in IoT terminals due to their advantages of low power consumption and open source. [0003] There are many studies abroad on the RISC-V instruction set, and a variety of open source RISC-V processors have been designed and widely...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/38G06F9/30G06F7/57
CPCG06F9/3867G06F9/3846G06F7/57G06F9/30069
Inventor 康明才顾佳浩
Owner NANJING UNIV OF SCI & TECH
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