A self-accelerating locked phase-locked loop

Abstract

The invention discloses a self-accelerating locked phase-locked loop, which comprises a frequency and phase detector, a charge pump, a low-pass filter, a voltage-controlled oscillator, a frequency divider, a rectifier, a filter, and a bandwidth control circuit. The frequency and phase detector, the charge pump, the low-pass filter, and the voltage-controlled oscillator are connected in sequence, and the output of the voltage-controlled oscillator is fed back to one input terminal of the frequency and phase detector through the frequency divider, and the other of the frequency and phase detector One input terminal is connected to a reference frequency source. The output terminal of the frequency and phase detector is also connected to the input terminal of the rectifier, and the rectifier, filter, and bandwidth control circuit are connected in sequence, and the bandwidth control circuit is used to generate a control word signal proportional to the output signal of the frequency and phase detector and input it to the low The pass filter controls the number of capacitors connected in the parallel capacitor array of the low-pass filter to control the bandwidth, so as to realize the accelerated locking of the phase-locked loop to the reference frequency.

Description

technical field [0001] The invention relates to a phase-locked loop structure. Background technique [0002] With the continuous improvement of the performance of the integrated circuit, the frequency of the chip is gradually increasing, but due to the limitation of the printed circuit board technology, it becomes more and more difficult to provide a higher frequency clock signal to the chip through the outside. Therefore, inside the chip, It is very important to generate a stable clock. Phase-locked loops (Phase-locked loops, PLL) is a frequency and phase synchronization technology that uses the principle of feedback control. Its function is to synchronize the clock output by the circuit with its external reference clock. When the frequency or phase of the reference clock changes, the phase-locked loop will detect this change and adjust the output frequency through its internal feedback system until the two are re-synchronized. This synchronization is also called "phase-lo...

AI Technical Summary

Problems solved by technology

In many application scenarios, the frequency required by integrated circuits is not single, and frequency hopping may be required according to needs. How to quickly lock after frequency hopping brings challenges to PLL design

Some circuits have complex application scenarios, and external interference will affect the frequency locking effect, causing the phase-locked loop to lose lock. Under the action of negative feedback adjustment, how to restore the locked frequency is also a difficult problem

[0003] In the prior art, there are methods that add more charging branches in the charge pump, which will cause additional power consumption and noise; there are methods that rely on digital assistance technology, and this method will cause more serious noise problems

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