Noise high power supply rejection ratio circuit

Abstract

The invention relates to the technical field of electronics, in particular to a noise high power supply rejection ratio circuit. The noise high power supply rejection ratio circuit comprises: a first-stage amplification circuit consisting of an operational amplifier and a capacitor C1; a second-stage amplifying circuit consisting of MOS (Metal Oxide Semiconductor) transistors M2, M3, M4, M5, M6, M7, M8 and MPS, a resistor RC and capacitors C and CC; and a third-pole amplifying circuit consisting of MOS (Metal Oxide Semiconductor) tubes M1 and MP, capacitors Cpar, CO and Cb and resistors Resr and RL. The output end of the operational amplifier in the first-stage amplifying circuit is connected to the grid electrode of the MOS tube M6 in the second-stage amplifying circuit, the grid electrode of the MOS tube MPS in the second-stage amplifying circuit is connected with the grid electrode of the MOS tube MP in the third-stage amplifying circuit, and the grid electrode of the MOS tube M2 in the second-stage amplifying circuit is connected with the grid electrode of the MOS tube M1 in the third-stage amplifying circuit. On the basis, a relatively high PSRR and a relatively good bandwidth are realized.

Description

technical field [0001] The invention relates to the field of electronic technology, in particular to a circuit with high noise and high power rejection ratio. Background technique [0002] With the continuous development of electronic products, power management solutions continue to pursue high efficiency, small area, and low cost. The LDO (Low Drop out) linear regulator has been widely used in various mobile electronic systems, such as notebook computers, cellular Telephones, pagers, PDAs, etc. It can greatly reduce the saturation voltage of the output transistor, so that the input voltage can be very close to the output voltage, thereby reducing power consumption and extending battery life. However, in the prior art, the suppression ratio circuit introduces a zero point through the series resistance of an external capacitor to offset a pole to achieve loop stability. Since the main pole value is proportional to the load resistance, the change of the output current will c...

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Problems solved by technology

However, in the prior art, the suppression ratio circuit introduces a zero point through the series resistance of an external capacitor to offset a pole to achieve loop stability. Since the main pole value is proportional to the load resistance, the change of the output current will change the loop. Second, the parasitic resistance of the output capacitor is easily affected by temperature, etc., which makes the zero-point and pole-offset invalid, so the stability deteriorates

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