Asynchronous reset D flip-flop

Abstract

The invention discloses an asynchronous reset D flip-flop. The asynchronous reset D flip-flop comprises a first latch and a second latch, wherein the first latch is provided with a first input end, a first clock signal end and a first output end, and the first input end serves as the input end of the asynchronous reset D flip-flop; and the second latch is provided with a second input end, a second clock signal end and a second output end, the first output end of the first latch is connected with the second input end of the second latch, and the second input end serves as the output end of the asynchronous reset D flip-flop. According to the asynchronous reset D flip-flop provided by the invention, the asynchronous reset D flip-flop formed by the transmission gate can eliminate the failure risk caused by the transmission gate, so that a required output value can be stably obtained, and a better use effect is realized; and then the D flip-flop can be better used as a basic composition unit of a sequential circuit to work for the circuit, and an ideal use effect is achieved.

Description

technical field [0001] The invention belongs to the technical field of electronic circuits, and relates to a flip-flop, in particular to an asynchronous reset D flip-flop. Background technique [0002] D flip-flop is the basic unit of sequential circuit, has memory function, and can be used for digital signal registration, shift register, frequency division and other functions, that is, to use the stored digital information for subsequent logic control, so it is widely used in large-scale and VLSI. The performance of the D flip-flop has a great influence on the whole system. [0003] D flip-flop reset methods can usually be divided into two categories: synchronous reset and asynchronous reset. The synchronous reset mode means that the reset signal is synchronized with the clock. The reset signal can only reset when the rising edge of the clock arrives, otherwise the system cannot be reset. The asynchronous reset mode means that no matter whether the clock edge arrives, the...

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Problems solved by technology

Both have their own advantages and disadvantages. Synchronous reset is effective only when the effective level of the clock arrives, so it can filter out the burr higher than the clock frequency, and can make the designed system a complete synchronous sequential circuit; the structure of asynchronous reset is simple, It is convenient to use the FPGA global reset port; in synchronous reset, only when the effective duration of the reset signal is longer than the clock cycle can it be recognized and reset, and since most DFFs in the target device library only have an asynchronous reset port, it is necessary to Additional combinational logic takes up more logic resources; asynchronous reset is susceptible to glitches. When the reset signal is released, if it is just near the active edge of the clock, it is prone to competition risks, metastable states, etc., metastable State means that the trigger cannot reach a determinable state within a specified period of time

The D flip-flop cannot transmit the logic signal correctly, indicating that the D flip-flop has a failure problem at this time, which may have a very important impact on the subsequent circuit

[0010] In the same way, taking the logic value of the input terminal D of the D flip-flop collected at the rising edge of the previous clock signal as 0 as an example, at the moment when the above-mentioned risk occurs, the output terminal of the first latch 10 will show The phenomenon of high-level glitches, which may also cause the state of the first latch 10 locked in the loop to flip, and then cause the logic state of the output terminal of the D flip-flop to be wrong, which will also cause the D flip-flop to appear failure problem

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