Manufacturing method of grain packaging structure

Abstract

The invention discloses a method for manufacturing a grain package structure. The method includes the following operations. A conductive substrate having a plurality of recesses is provided. Crystal grains are arranged in the grooves. A conductive layer is formed to cover the crystal grains and the conductive substrate; A patterned photoresist layer is formed on the conductive layer, wherein the patterned photoresist layer is provided with a plurality of openings to expose a plurality of areas of the conductive layer. A shield is formed on each region of the conductive layer. After the shield is formed, the patterned photoresist layer is removed. The conductive layer and the conductive substrate thereunder are selectively etched to a predetermined depth using the shield so as to form a plurality of conductive bumps and a plurality of electrodes, the remaining conductive substrate includes a base plate on which the electrodes are located, and the conductive bumps are located on the die. An upper sealing glue layer is formed to cover the bottom plate and the crystal grains, wherein the shield, the conductive bumps or the electrodes are exposed out of the upper sealing glue layer. According to the invention, the miniaturization of the crystal grain packaging structure in the vertical direction can be achieved, and the heat dissipation effect of a power chip can be improved.

Description

technical field [0001] The invention relates to a manufacturing method of a packaging structure, in particular to a manufacturing method of an embedded die packaging structure. Background technique [0002] With the popularization of consumer electronic products, such as mobile phones, tablet computers, notebooks, etc., consumers' demand for high functionality and small size of electronic products is becoming more and more obvious. The chip packaging process is an important step in the process of forming electronic products. In order to reduce the size of the chip package and further improve the performance of the chip package has become an important issue. [0003] The traditional packaging process is to package the semiconductor die cut from the wafer one by one. In addition to die bonding, the process also includes wire bonding, molding, etc., which is quite time-consuming. It takes a lot of work. Furthermore, the traditional method is to electrically connect the power...

AI Technical Summary

Problems solved by technology

[0003] The traditional packaging process is to package the semiconductor die cut from the wafer one by one. In addition to die bonding, the process also includes wire bonding, molding, etc., which is quite time-consuming. laborious

Furthermore, the traditional method is to electrically connect the power chips in the power module by bonding wires. The heat generated by the power chips is not easily dissipated effectively.

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