Chip test method and system and readable storage medium

Abstract

The invention provides a chip test method and system and a readable storage medium, the system comprises an upper computer and a test board, and a basic chip is carried on the test board; the method comprises the following steps: establishing communication connection between a basic chip and an upper computer, and downloading a predetermined functional program from the basic chip to form a chip to be tested; the upper computer adds a kernel support file and a test verification program which are selected and configured from a kernel support file library and a test verification program library to an inherent program module to form a test program corresponding to a chip to be tested, the test program is issued to the chip to be tested, and when configuration parameters are received, the configuration parameters are generated into test cases; and the chip to be tested drives the test program and the function program to run, starts a test task of the test verification program in the test program according to a test case issued by the upper computer, and tests the function realized by running the function program on the chip to be tested. According to the method, the generation efficiency of the test code is improved, and integrity verification of chip design can be quickly realized.

Description

technical field [0001] The invention relates to the technical field of testing, in particular to a chip testing method, system and readable storage medium. Background technique [0002] With the development of electronic technology, chips such as Field Programmable Gate Array (FPGA) are more and more widely used. Moreover, in the chip design process, the functions of the chip are often written into codes and burned into the chip to verify the functional integrity of the chip design. However, in the existing functional verification of chip design, due to the different functions of different types of chips, the functional codes used for testing are also different. At the same time, different code writers have different ways of writing codes, making it difficult to be compatible with each other. As a result, for different types of newly developed chips, it is usually necessary to write new test codes, resulting in a lot of energy spent on code writing; moreover, it also takes ...

AI Technical Summary

Problems solved by technology

However, in the existing functional verification of chip design, due to the different functions of different types of chips, the functional codes used for testing are also different; at the same time, different code writers have different ways of writing code, which is difficult to be compatible with each other.

As a result, for different types of newly developed chips, it is usually necessary to write new test codes, resulting in a lot of energy spent on code writing; moreover, it also takes a lot of time to install, disassemble and record operations in the testing process of different types of chips. Time and energy greatly increase the time-consuming and workload of test verification

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