Regional parallel loading device and method for tensor data

Abstract

The invention provides a regional parallel loading device and method for tensor data. The device comprises a parallel input register array which is used for providing a rapid register area for data rearrangement for an input feature map in an input cache; and a parallel input data access engine used for carrying out regionalized parallel access on the data in the parallel input register array. After the design is adopted, the structure of a connecting circuit can be simplified, so that the area and the power consumption of a chip are optimized.

Description

technical field [0001] The invention belongs to the field of computer hardware and artificial neural network algorithm deployment hardware acceleration, and the field of digital integrated circuit design, and specifically relates to a key processing device for input data of a deep convolutional neural network hardware acceleration chip, and a design method thereof. Background technique [0002] The deep convolutional neural network algorithm is composed of multiple layers of specific neuron algorithm layers and hidden layers, mainly including convolutional layers, and the main operator is convolution calculation of matrix or vector. The main characteristics of this computing task are the large amount of input data, the coupling of the input data with spatial feature information, and the data calculated by each convolution often overlaps with the already calculated data, and the input data is often data in tensor format. The required calculation data is extracted with a certa...

AI Technical Summary

Problems solved by technology

The invention of patent 4 is too coupled with the design of the central processing unit, and the design and implementation complexity is too high

Images