Near-threshold circuit delay estimation method based on polynomial chaos Kriging element model

Abstract

The invention discloses and protects a near-threshold circuit delay estimation method based on a polynomial chaos Kriging element model, which considers the influence of process parameter fluctuation increase under a near-threshold voltage, constructs a model from process parameters to circuit delay through the polynomial chaos Kriging element model, and further performs yield evaluation on circuit path delay. The accurate and effective time sequence analysis method under the near-threshold voltage is realized, and guidance is provided for circuit design. Firstly, a key path of a circuit is extracted through a tool PrimeTime, efficient sampling is carried out on the circuit through Latin hypercube, then delay of the key path is obtained through SPICE simulation under different technological parameter conditions, delay data of non-Gaussian distribution are converted into data conforming to Gaussian distribution through generalized power transformation and maximum likelihood estimation, and a path delay model under low voltage is built by using a polynomial chaos Kriging element model; and finally the time sequence yield evaluation of the circuit is finished.

Description

technical field [0001] The invention belongs to the field of integrated circuit design automation (EDA), in particular to a near-threshold circuit delay estimation method based on a polynomial chaotic Kriging element model. Background technique [0002] Modern Internet of Things and mobile terminal devices have greatly increased the demand for chip processing data volume and standby time. Therefore, how to reduce the chip's data processing power consumption and improve energy efficiency has become a key issue in chip design. Traditional low power consumption technology utilizes the law that power consumption decreases with the square relationship of voltage, and reduces power consumption by reducing the power supply voltage. Subthreshold circuit design greatly reduces circuit power consumption by reducing the supply voltage below the threshold voltage. This method is applied to devices that do not require high performance but require extremely low power consumption, such as...

AI Technical Summary

Problems solved by technology

However, there are some shortcomings in the design of sub-threshold circuits: on the one hand, because the performance of chips near the sub-threshold voltage decreases exponentially compared with conventional voltages, this makes sub-threshold circuits unable to meet the calculation speed requirements of some applications; on the other hand , at extremely low voltage, the leakage power consumption increases greatly and becomes the main source of power consumption at the subthreshold voltage, which weakens the power consumption advantage of the circuit at the subthreshold voltage

As the supply voltage decreases, the delay fluctuation increases under process deviation, and the traditional timing analysis method will cause serious performance loss, which is no longer suitable for the timing analysis of near-threshold circuits under process deviation.

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