Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Method for quickly obtaining node simulation state in digital gate level circuit

A technology of gate-level circuits and internal nodes, which is applied in the field of quickly obtaining the simulation state of internal nodes of digital gate-level circuits, which can solve the problems of long time consumption, complexity, and inconvenient gate-level circuits, so as to improve accuracy and reduce complexity , the effect of reducing the simulation time

Active Publication Date: 2017-10-17
XIDIAN UNIV
View PDF7 Cites 15 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

When using traditional simulation tools for simulation verification, it is necessary to write test code files for each reference circuit separately, which is very inconvenient for large gate-level circuits
Although the existing gate-level netlist simulator solves this problem very well, with the development of SoC design techniques and more and more diverse application requirements, the SoC architecture is becoming more and more complex, and the chip scale is becoming more and more complex. Huge, the simulation difficulty of existing simulators is getting more and more difficult, and the time consumed is getting longer and longer, which seriously hinders the progress of verification work

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Method for quickly obtaining node simulation state in digital gate level circuit
  • Method for quickly obtaining node simulation state in digital gate level circuit

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0022] In order to make the object, technical solution and advantages of the present invention more clear, the present invention will be further described in detail below with reference to the accompanying drawings and examples.

[0023] Refer to attached figure 1 , the gate-level circuit targeted by the present invention includes 4 external input terminals G0, G1, G2, G3, 6 D flip-flops DFF nodes DFFG4, DFFG5, DFFG6, DFFG7, DFFG8, DFFG9, 3 NOT gates NOT nodes NOTG15, NOTG16, NOTG20, 1 AND node ANDG19, 2 OR nodes ORG17, ORG18, 4 NOR nodes NORG11, NORG12, NORG13, NORG14, 1 NAND node NANDG10 and 2 external outputs G21 , G22.

[0024] Refer to attached figure 2 , the present invention is based on the key node extraction method of gate-level circuit simulation, comprises the following steps:

[0025] Step 1: According to figure 1 Given a gate-level circuit, the connection relationship between the external input, external output and internal nodes of the gate circuit is obtain...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention discloses a method for quickly obtaining a node simulation state in a digital gate level circuit, and mainly solves the problems of high difficulty and long time consumption on the aspect of gate level netlist simulation verification in the prior art. The method comprises the following steps that: 1) according to a given gate level circuit, obtaining a connection relationship between the external input and the external output of the gate level circuit and an internal node; 2) describing the logic relationship of the gate level circuit with a hardware language to generate a gate level circuit logic description file; 3) according to the connection relationship in 1), converting the gate level circuit into an RTL (Register-Transfer Level) description unit; 4) according to the connection relationship of the gate level circuit, generating a simulation test file with a software language; and 5) adding the files generated from S2) to S4) into commercial simulation software to be simulated to obtain the simulation state of the internal node of the gate level circuit. By use of the method, simulation complexity and time can be greatly reduced, gate level netlist simulation verification is improved, and the method can be used for extracting gate level netlist key nodes and accelerating the gate level netlist simulation verification.

Description

technical field [0001] The invention belongs to the technical field of circuit processing, and in particular relates to a method for quickly acquiring the simulation state of internal nodes of a digital gate-level circuit, which can be used in the tracking signal extraction stage in post-silicon verification based on simulation. Background technique [0002] As is well known in the industry, the design of integrated circuit chips is roughly divided into two parts: front-end logic design synthesis and back-end physical design synthesis. The front-end logic design includes basic RTL programming and simulation, logic synthesis, static timing analysis STA and formal verification and other steps; the back-end physical design includes clock tree synthesis, layout and routing, power analysis, physical verification and design for manufacturability Wait for multiple steps. In chip design, the definition, development, synthesis, integration, and verification of front-end logic are im...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/50
CPCG06F30/33G06F30/39
Inventor 潘伟涛董勐周俊邱智亮付新宇
Owner XIDIAN UNIV
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products