Chip back-end revision method, device and computer equipment based on function buffer

Abstract

The application discloses a chip back-end revision method, device, computer equipment, and storage medium based on functional buffers, including: obtaining the original list of each electronic unit in the process file; searching for each electronic unit in the preset digital process library according to the original list; The spare unit of the electronic unit, and generate a substitute list according to the key-value pair relationship between each electronic unit and its corresponding spare unit; analyze the process file according to the preset design tool, and extract the illegal file in the process file; find the violation in the substitute list The target backup unit corresponding to the unit, and form a map file according to the target backup unit and the violation file; confirm the violation type of the violation file according to the preset violation rules, and generate a script file for the design tool to run according to the map file and violation type; run the design The tool executes the script file so that the target spare unit replaces the violating unit to complete the modification of the recipe file.

Description

technical field [0001] Embodiments of the present invention relate to the field of chip manufacturing, in particular to a method, device, computer equipment, and storage medium for chip backend revision based on functional buffers. Background technique [0002] In the design of modern integrated circuits, especially the design of the digital logic part, in order to prevent new problems from being found in the test after the chip is produced, a lot of spare dummy cells (spare units) are generally evenly placed in the entire digital logic area, and the chip is revised later. In the process, only a few layers of metal need to be moved to change or repair the function of the chip. [0003] As for functional changes in the digital logic part, especially the post mask ECO stage (the transistors of the chip have been processed, but the engineering modification during the transistor connection has not been done), since the position and direction of all spare units cannot be changed ...

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Problems solved by technology

[0003] As for functional changes in the digital logic part, especially the post mask ECO stage (the transistors of the chip have been processed, but the engineering modification during the transistor connection has not been done), since the position and direction of all spare units cannot be changed , so we can only rely on the existing spare unit, modify the design function by modifying the digital netlist or the corresponding EDA (Electronic design automation, electronic design automation) tool command, and correspondingly reflect the timing and timing caused by the back-end physical design. design violations etc.

How to fix issues such as timing and design violations by inserting spare cells, the traditional processing method is to modify the digital netlist according to each violation point, including finding the position of the alternate spare cell, changing the signal point of the violation point and the alternate spare cell The hierarchical connection relationship among them, etc., and repeat this process many times until the design converges. It is obvious that this ECO (Engineering Change Order, engineering modification) method is inefficient and error-prone

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