Integrated circuit time delay detection method and device, storage medium and electronic equipment

Abstract

The invention provides an integrated circuit time delay detection method and device, a storage medium and electronic equipment. The integrated circuit time delay detection method comprises the following steps: acquiring a circuit netlist and a circuit layout of a to-be-detected target integrated circuit; acquiring a selected target wire, and acquiring a specified circuit area in the circuit layout based on the target wire; performing parasitic parameter extraction on the specified circuit area according to the circuit netlist to obtain a simplified DSPF netlist file; performing simulation according to the simplified DSPF netlist file to obtain a first time delay of the target wire in the specified circuit area; and according to the first time delay, calculating the target time delay when the target wire is in any length. Therefore, the target time delay of the target wire with any length or after length change can be calculated only through one-time simulation, the simulation frequency can be reduced, and the efficiency can be improved.

Description

technical field [0001] The present application relates to the field of integrated circuit simulation testing, in particular to an integrated circuit delay detection method, device, storage medium and electronic equipment. Background technique [0002] In IC design, there are parasitic parameters that are not required by the design between the interconnection lines, that is, the so-called parasitic parameters. The parasitic parameters include parasitic resistance, capacitance and inductance. In the circuit layout (layout), the distribution of parasitic resistance and parasitic capacitance is complex and dense. As the scale and complexity of circuit layout and layout and routing continue to expand and increase, the parasitic parameter files extracted by EDA tools are also getting larger and larger. In particular, for Memory (memory), there are various repeated units in its circuit layout, and there are many traces and MOS transistors in each unit. If its layout is not simpli...

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Problems solved by technology

However, when the length of the trace changes, it is necessary to simulate the delay again, which increases the burden of the simulation process and is not conducive to the improvement of efficiency.

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