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Memory addressing segmentation method and device

A cutting device and addressing technology, applied in the fields of instruments, electrical digital data processing, etc., can solve problems such as signal quality problems, and achieve the effect of low-cost manufacturing

Pending Publication Date: 2021-04-23
FUZHOU ROCKCHIP SEMICON
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

During the read operation, the 4DQ memories of different manufacturers share one DQS and encounter signal quality problems

Method used

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  • Memory addressing segmentation method and device
  • Memory addressing segmentation method and device

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Embodiment Construction

[0017] In order to explain in detail the technical content, structural features, achieved goals and effects of the technical solution, the following will be described in detail in conjunction with specific embodiments and accompanying drawings.

[0018] This article will introduce a memory addressing segmentation method, including the following steps, S100: Before the bus access command to the memory controller is output to the memory controller, the addressing unit performs the first address information in the access command according to the corresponding mapping relationship. The invalid bits are filled to obtain the second address information, and the second address information is transmitted to the memory controller. The access instruction may include content such as packet header, packet trailer, and key. Specifically, it also has the location of a particle in the memory that needs to be accessed in the entire memory, which can be called the first address information. The ...

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Abstract

The invention discloses a memory addressing segmentation method and device, and the method comprises the following steps: enabling an addressing unit to carry out the invalid bit filling of first address information in an access instruction according to a corresponding mapping relation before the access instruction of a bus to a memory controller is outputted to the memory controller, obtaining second address information, and transmitting the second address information to the memory controller. According to the scheme, the memory controller does not need to know the specific size of the memory connected with the memory controller and only needs to input the content of the memory according to the second address information from the addressing unit for searching. And low-cost manufacturing of the memory is facilitated.

Description

technical field [0001] The invention relates to the field of chip design, in particular to an instruction processing method compatible with memory of different sizes. Background technique [0002] For memory chips in the prior art, a memory controller is usually used to control different memory particles. Take the memory controller as an example with a 32-bit width. The 32 IOs are usually connected to 8*4 groups of different particles, and each particle uses a DQS (input and output synchronous clock). If cost reduction is required, 4 DQs are also used. The method of memory granules, under normal circumstances, requires the DQS of the memory controller to be connected to the DQS of two granules at the same time. During the read operation, if 4DQ memories from different manufacturers share one DQS, they will encounter signal quality problems. Contents of the invention [0003] Therefore, it is necessary to provide an application method that is compatible with memory module...

Claims

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Application Information

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IPC IPC(8): G06F13/16
CPCG06F13/1694
Inventor 汤云平
Owner FUZHOU ROCKCHIP SEMICON
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