Single-particle soft error processing method for ensuring content consistency of Cache and off-chip memory

Abstract

The invention discloses a single-particle soft error processing method for ensuring content consistency of a Cache and an off-chip memory. The method comprises the following steps: setting a refreshing address as a first address of the memory; reading refreshing address content according to words; when it is determined that the single-particle soft error is triggered, reading a processor error state register; when it is determined that the current single-particle soft error is a correctable error, correcting an error address corresponding to the current single-particle soft error, and writinga correction result back to the memory; performing 4-byte accumulation on the refreshing address; and when it is determined that the refreshing address after 4-byte accumulation exceeds the effectiveaddress range of the memory, returning to execute the step of setting the refreshing address as the head address of the memory. When single event soft errors such as illegal instruction traps and dataaccess traps are caused by the single event effect, measures such as clearing instruction Caches and data Caches of corresponding cores are adopted to adapt to operation characteristics of a processor when enabling the Caches, and content consistency of the Caches and an off-chip memory when the single event soft errors occur is guaranteed.

Description

technical field [0001] The invention belongs to the field of aerospace technology, and in particular relates to a single-event soft error processing method for ensuring the content consistency between a Cache and an off-chip memory. Background technique [0002] During the operation of the spacecraft in orbit, electronic components such as memories will be affected by the radiation environment of space particles, which will cause problems such as single event flipping, which will lead to single event soft errors such as instruction access traps, data access traps, and illegal instruction traps in the system, seriously affecting the aerospace industry. normal function and service of the server. Therefore, in order to ensure the highly reliable operation of the system, the on-board operating system must have appropriate software error handling capabilities to ensure the normal execution of user programs and the display of system performance. [0003] Especially in the field o...

AI Technical Summary

Problems solved by technology

Compared with the previous software that does not enable the processor Cache function, after the processor Cache is enabled, the single event soft error handling of the operating system faces a new problem, that is, the contents of the Cache and the off-chip memory are inconsistent when a single event error occurs

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