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A cake-type integrated circuit layout method and system for chips

A technology of integrated circuits and layout methods, applied in CAD circuit design, electrical digital data processing, special data processing applications, etc., can solve the problems of increasing the difficulty of chip area reduction, affecting the aesthetics of chip layout, and increasing the difficulty of integrated circuits, etc.

Active Publication Date: 2021-07-06
广芯微电子(苏州)有限公司
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  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

According to the layout of traditional integrated circuit layout principles, it will not only greatly increase the difficulty of reducing the area of ​​the chip, but also lead to messy and complex layout of the chip layout, which will affect the overall aesthetics of the chip layout and increase the number of follow-up R&D personnel to organize and integrate. circuit difficulty

Method used

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  • A cake-type integrated circuit layout method and system for chips
  • A cake-type integrated circuit layout method and system for chips
  • A cake-type integrated circuit layout method and system for chips

Examples

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no. 1 example

[0044] see Figure 1-3 .

[0045] like figure 1 As shown, this embodiment provides a cake-type integrated circuit layout method for chips, which at least includes the following steps:

[0046] S101. After obtaining the circuit network information netlist provided by the chip front end, perform correlation analysis, and obtain a function correlation table and a logical correlation table among several registers.

[0047]Specifically, for step S101, the netlist netlist provided by the front end is obtained, wherein the netlist netlist is the circuit network information, including the cell (unit) information used in the circuit and the connection relationship between them, which also conforms to the Verilog syntax, from The function description of each module in the netlist netlist analyzes the logical relationship of each module (or register), and further determines the correlation between functions or logic of each module (register), such as the input terminal input of each mo...

no. 2 example

[0068] see Figure 4 .

[0069] like Figure 4 As shown, this embodiment provides a cake-type integrated circuit layout system for chips, including:

[0070] The correlation analysis module 100 is used for obtaining the circuit network information netlist provided by the chip front end and performing correlation analysis to obtain a function correlation table and a logical correlation table among several registers.

[0071] Specifically, for the association analysis module 100, the netlist netlist provided by the front end is obtained, wherein the netlist netlist is the circuit network information, including the cell (unit) information used in the circuit and the connection relationship between them, which also conforms to Verilog syntax , analyze the logical relationship of each module (or register) from the functional description of each module in the netlist netlist, and further determine the correlation between functions or logic of each module (register), such as the in...

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Abstract

The invention discloses a cake-type integrated circuit layout method and system for a chip. The method includes: obtaining a circuit network information netlist provided by the front end of the chip, and performing correlation analysis to obtain a function correlation table and a function correlation table between several registers. Logical association table; determine the corresponding standard cell library according to each functional module used in the chip layout, and sort according to the area size of the functional modules; according to the functional association table, logical association table and the described The standard cell library, combined with the principle of placing the chip on the boundary, divides the chip into several functional areas and then performs a cake-like layout of the chip. The present invention adopts a unique chip cake layout method to improve the flexibility of the layout of functional modules with a large number and different sizes during layout, avoid messy and complicated problems in chip layout, and reduce the area required for chip layout. Effective use of wiring resources and increase the routing rate, reducing the cost of chip layout.

Description

technical field [0001] The present invention relates to the technical field of integrated circuits, and in particular, to a method and system for the layout of a cake-type integrated circuit for chips. Background technique [0002] The layout of integrated circuit wiring is a crucial part of the digital circuit design process. It has an important impact on whether the timing of the chip is met, the area of ​​the chip, and the final yield of the chip. It also directly affects the cost of chip tape-out. Especially when the chip reaches a certain scale, due to the need to use more and different sizes of IP modules, macro modules and standard cells for mixed design, and in this case, the IP modules and macro modules can be reasonably handled to improve the efficiency of the design. To meet the timing and power supply requirements well, while reducing the chip area, will become a key technical point in the digital circuit design process. The existing integrated circuit principle...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F30/392G06F115/08
CPCG06F30/392G06F2115/08
Inventor 王锐谭钰鑫李建军王亚波莫军
Owner 广芯微电子(苏州)有限公司
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