Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Power chip preparation method and power chip

A power chip and drift layer technology, which is applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve problems such as complex processes, achieve simple processes, improve over-current shutdown capabilities, and reduce electric field strength.

Pending Publication Date: 2020-12-11
GLOBAL ENERGY INTERCONNECTION RES INST CO LTD +2
View PDF0 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] In order to overcome the shortcomings of the above-mentioned complex process in the prior art, the present invention provides a method for preparing a power chip, including:

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Power chip preparation method and power chip
  • Power chip preparation method and power chip

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0055] Embodiment 1 of the present invention provides a method for preparing a power chip, the specific flow chart is as follows figure 1 As shown, the specific process is as follows:

[0056] S101: forming an N-type stop ring 41 on the front of the N-drift layer 1;

[0057] S102: Form a transition region 3 and a P-type withstand voltage ring 42 on the front of the N-drift layer 1 according to different doping concentrations;

[0058] S103: forming an active region 2 on the front surface of the N-drift layer 1;

[0059] The doping concentration of the transition region 3 near the active region 2 is greater than the doping concentration near the P-type voltage-sustaining ring 42 , and the doping depth of the transition region 3 near the active region 2 is greater than the doping depth near the P-type voltage-sustaining ring 42 .

[0060] Among them, the resistivity and thickness parameters of the N-material used in the N-drift layer 1 are closely related to the breakdown volta...

Embodiment 2

[0094] Embodiment 2 of the present invention provides a power chip prepared by using the power chip preparation method of Embodiment 1, such as figure 2 As shown, it includes an N-drift layer 1, an active region 2, a transition region 3, an N-type stop ring 41 and a P-type voltage-resistant ring 42; the N-type stop ring 41 and the P-type voltage-resistant ring 42 form a terminal region 4;

[0095] The active region 2, the transition region 3, the N-type stop ring 41 and the P-type voltage-resistant ring 42 are all located on the front of the N-drift layer 1, the N-type stop ring 41 is located at the edge of the N-drift layer 1, and the P-type voltage-resistant ring 42 is located between the transition zone 2 and the N-type stop ring 41;

[0096] The transition region 3 is formed according to different doping concentrations, and the doping concentration of the transition region 3 close to the active region 2 is greater than the doping concentration close to the P-type withstan...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

PropertyMeasurementUnit
thicknessaaaaaaaaaa
thicknessaaaaaaaaaa
Login to View More

Abstract

The invention provides a power chip preparation method and a power chip. The method comprises: forming an N-type cut-off ring (41) on the front surface of an N-drift layer (1), forming a transition region (3) and a P-type withstand voltage ring (42) on the front surface of the N-drift layer (1) according to different doping concentrations, and forming an active region (2) on the front surface of the N-drift layer (1), wherein the doping concentration of the transition region (3) close to the active region (2) is larger than the doping concentration of the transition region (3) close to the P-type voltage-withstanding ring (42), and the doping depth of the transition region (3) close to the active region (2) is larger than the doping depth of the transition region (3) close to the P-type voltage-withstanding ring (42). According to the power chip, the gradient doped transition region (3) is formed on the front surface of the N-drift layer (1) through different doping concentrations, sothat improvement of electric field distribution of the transition region is facilitated, the electric field intensity can be effectively reduced, the hole current density of the transition region whenthe IGBT is turned off is reduced, the region is prevented from being burnt by heat, the overcurrent turn-off capability is improved, and the firmness of the IGBT power chip is improved.

Description

technical field [0001] The invention relates to the technical field of semiconductor devices, in particular to a method for preparing a power chip and the power chip. Background technique [0002] In power chips such as metal-oxide semiconductor field effect transistors (Metal Oxide Semiconductor, MOSFET) or insulated gate bipolar transistors (Insulated Gate Bipolar Transistor, IGBT), there is a transition zone structure similar to a diffusion guard ring at the outermost cell , that is, the transition region structure is a region between the active region and the terminal region of the power chip; it is also called the main junction. [0003] In the case of high-current shutdown of inductive loads, the IGBT power chip is easily burned in the transition zone. The main reason is that during the turn-off transient process, there is uneven distribution of current, electric field and heat inside the entire IGBT power chip; especially in the transition area, it is easy to form el...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/331H01L29/739H01L29/06
CPCH01L29/0619H01L29/66348H01L29/7397
Inventor 刘江高明超金锐
Owner GLOBAL ENERGY INTERCONNECTION RES INST CO LTD
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products