Preparation method for improving performance of SOI device

Abstract

The invention provides a preparation method for improving the performance of an SOI device, and the method comprises the steps of providing an SOI structure which comprises matrix silicon, a buried oxide layer located on the matrix silicon and surface silicon located on the buried oxide layer, forming a silicon film layer with the thickness of 2nm on the surface silicon, and enabling the silicon film layer and the surface silicon to form an insulating silicon layer; enabling part of the insulating silicon layer on the surface of the SOI structure to react to form a silicon oxide film layer; and forming a pseudo gate structure of a PMOS on the silicon oxide thin film layer, wherein the pseudo gate at least comprises a gate oxide layer, a polycrystalline silicon layer located above the gateoxide layer, and a first side wall attached to the side wall of the polycrystalline silicon layer. By adopting epitaxial silicon growth and a furnace tube process, on one hand, the consumption of insulating silicon can be reduced, germanium-silicon growth is facilitated, and a contact hole is prevented from being punctured; on the other hand, the problem of alignment offset caused in the photoetching process is solved, contact hole offset is avoided, and the device can work normally.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a preparation method for improving the performance of an SOI device. Background technique [0002] With the development of silicon integrated circuit technology, many methods are used to improve device performance. Fully depleted silicon-on-insulator has an ultra-thin insulating layer (buried oxide layer), which can realize dielectric isolation of components in integrated circuits and completely eliminate the latch-up effect in substrate silicon CMOS circuits. Among them, fully depleted silicon-on-insulator devices are considered to be a promising new type of planar devices due to their low power consumption, high speed, high integration density, and simple process. [0003] In the manufacturing process of fully depleted silicon-on-insulator (FD-SOI) devices, the source and drain electrodes of PMOS are grown on silicon-on-insulator (SOI) silicon germanium (SIGE). (SOI). ...

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Problems solved by technology

[0006] In view of the above-mentioned shortcomings of the prior art, the object of the present invention is to provide a preparation method for improving the performance of SOI devices, which is used to solve the problem of contact hole perforation caused by excessive consumption of insulating silicon in the preparation of fully depleted insulator devices in the prior art. , and the problem of alignment shift caused by thermal expansion during photolithography

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