Multiplier based on reverse polarity technology and code generation method thereof

Abstract

The invention discloses a multiplier based on a reverse polarity technology and a code generation method thereof. The multiplier comprises a partial product generation module, a partial product compression module and a carry-save adder; the partial product generation module calculates the multiplier and the multiplicand to obtain a partial product; the partial product compression module compressesthe partial product to obtain a partial product compression tree; and the carry-save adder performs addition processing on the signals connected to the carry-save adder in the compression process, and an addition processing result is connected to the output end of the multiplier; the partial product generation module adopts an NAND gate array, the partial product compression module adopts a Wallace tree structure, the compressor mainly adopts a reverse polarity full adder and a reverse polarity half adder, and a common full adder and a common half adder are adopted under specific conditions.By adopting the reverse polarity full adder with small area and low power consumption, the power consumption of the multiplier is effectively reduced, codes of the multiplier can be automatically generated, and the time sequence of the multiplier can be integrally optimized.

Description

technical field [0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a multiplier based on reverse polarity technology and a code generation method thereof. Background technique [0002] With the rapid development of big data, artificial intelligence and cloud computing technology, the demand for chip computing power is getting higher and higher, and an important factor that restricts chip computing power is power consumption. In order to solve the performance and power consumption problems, domestic and foreign The current research focuses on artificial intelligence chips. As a main component of artificial intelligence chips, the multiplier's performance and power consumption directly affect the performance and power consumption of the entire chip. Therefore, it is particularly important to design multipliers with high performance and low power consumption. [0003] Generally, the compressor is an important component unit ...

AI Technical Summary

Problems solved by technology

[0004] The compression process of the Wallace tree is usually done manually, its design is complex, and it is difficult to consider the timing as a whole, and after using the reverse polarity full adder and reverse polarity half adder, it will make the entire partial product The compression process becomes more complicated because the polarity of the signal and the type of compressor need to be considered during the compression process, as well as the arrival time of the signal and how to reasonably distribute the signal to the input pins of the compressor

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