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Image processing acceleration method, image processing model storage method and corresponding devices

An image processing and model technology, applied in the field of machine learning, to achieve the effect of improving the speed of the network

Pending Publication Date: 2020-10-27
ALIBABA GRP HLDG LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] This application provides an image processing acceleration method to solve the problem in the prior art that parallel computing cannot be realized without computing zero-weight multiplication operations

Method used

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  • Image processing acceleration method, image processing model storage method and corresponding devices
  • Image processing acceleration method, image processing model storage method and corresponding devices
  • Image processing acceleration method, image processing model storage method and corresponding devices

Examples

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no. 1 example

[0066] Please refer to figure 1 , which is a flow chart of an embodiment of an image processing acceleration method provided by the present application, where the execution body of the method includes an image processing acceleration device. An image processing acceleration method provided by this application includes:

[0067] Step S101: Obtain the input feature map of the convolutional layer in the image processing model.

[0068] The network structure of the image processing model includes a convolutional neural network (Convolutional Neural Networks, CNN). CNN is a type of feedforward neural network (Feedforward Neural Networks) that includes convolutional calculations and has a deep structure. It is one of the representative algorithms for deep learning. From the perspective of whether the network parameters are redundant, the convolutional neural network can be a sparse convolutional neural network (sparse CNN) or a non-sparse convolutional neural network (non-sparse C...

no. 2 example

[0131] Please see Figure 7 , which is a schematic diagram of an embodiment of the image processing acceleration device of the present application. Since the device embodiment is basically similar to the method embodiment, the description is relatively simple, and for relevant parts, refer to the part of the description of the method embodiment. The device embodiments described below are illustrative only.

[0132] The present application additionally provides an image processing acceleration device, including:

[0133] The input feature map acquisition unit 701 is used to acquire the input feature map of the convolutional layer in the image processing model;

[0134] A hardware computing unit allocation unit 703, configured to determine hardware computing units corresponding to each convolution kernel in the convolution layer from a plurality of hardware computing units;

[0135] The convolution operation unit 705 is used to determine the relationship between each convolut...

no. 3 example

[0160] Please refer to Figure 8 , which is a flowchart of an embodiment of the image processing model storage method of the present application. Since the method embodiment is basically similar to the first embodiment, the description is relatively simple, and for relevant details, please refer to the part of the description of the first method embodiment. The method embodiments described below are illustrative only.

[0161] A method for storing an image processing model in this embodiment includes the following steps:

[0162] Step S801: Obtain an image processing model based on a convolutional neural network to be stored.

[0163] The image processing model may include multiple convolutional layers, wherein the weight matrix of some convolutional layers is a sparse matrix, and the weight matrix of some convolutional layers is a dense matrix.

[0164] Step S803: For each non-zero weight of the image processing model, according to the non-zero weight, the row number and c...

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Abstract

The invention discloses an image processing acceleration method and device, and an image processing model storage method and device. The acceleration method comprises the steps of obtaining an input feature map of a convolution layer in an image processing model; determining a hardware operation unit corresponding to each convolution kernel in the convolution layer from the plurality of hardware operation units; determining a convolution result between each convolution kernel and the input feature map in parallel according to a non-zero weight in the convolution kernel and the input feature map through a hardware operation unit corresponding to each convolution kernel; and generating an output feature map of the convolution layer according to a convolution result. By adopting the processing mode, the convolution operation process does not need to consider the operation of zero weight, the weight coordinate does not need to be calculated, and the data flow does not have a data dependence relationship; therefore, the network operation speed can be effectively improved, and the method is suitable for sparse CNN and non-sparse CNN at the same time.

Description

technical field [0001] The present application relates to the technical field of machine learning, in particular to an image processing acceleration method and device, and an image processing model storage method and device. Background technique [0002] With the pursuit of high-efficiency models, the parameter matrices of many current deep neural networks can be converted into sparse matrices through sparse operations. Neural networks that use sparse matrices as parameter matrices are referred to as sparse networks. Since the non-zero parameters in the sparse network are usually non-redundant, almost all of these parameters contribute to the actual model results, so the use of a sparse network can not only ensure the accuracy of the model, but also reduce the consumption of the model on storage space and computing time. [0003] At present, hardware platforms running sparse networks are mainly hardware platforms such as Field Programmable Gate Array (FPGA) and custom chip (...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F7/523G06F7/544G06N3/04G06N3/063G06N3/08
CPCG06F7/523G06F7/5443G06N3/063G06N3/08G06N3/045
Inventor 林伟崔晓源张健松黄瑞瑞梁云卢丽强
Owner ALIBABA GRP HLDG LTD
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