Manufacturing method of lateral double-diffused transistor

Abstract

The invention relates to the technical field of semiconductors, and provides a manufacturing method of a lateral double-diffused transistor. The manufacturing method comprises the steps of forming a drift region in a substrate; forming a gate structure on the substrate, wherein the gate structure defines a source end region and a drain end region which are separated from each other, the gate structure includes a gate oxide layer and a polysilicon layer which are sequentially stacked on the substrate; forming a channel region in the substrate in the source end region, wherein the drift region is arranged around the channel region; and respectively forming a source region and a drain region in the source end region and the drain end region, and in the process of forming the source region inthe source end region, forming the source region with injection regions with different doping types and different doping concentrations through doping ion self-alignment injection by combining the side walls formed by a process for multiple times with the interval of the polycrystalline silicon layer above the source end region. Therefore, the distance of the polycrystalline silicon layer above the source end region can be reduced, the size of the formed device is reduced, and the source-drain on resistance is effectively reduced.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a method for manufacturing a lateral double-diffused transistor. Background technique [0002] As a type of power field effect transistor, laterally diffused MOS (Lateral Double-Diffused MOSFET, LDMOS) transistor has process compatibility, good thermal stability and frequency stability, high gain, low feedback capacitance and thermal resistance, and constant input impedance, etc. Excellent characteristics, so it has been widely used, and people have higher and higher performance requirements for LDMOS. [0003] The LDMOS device is a key component of the entire power integrated circuit, and its structural performance directly affects the performance of the power integrated circuit. The main parameters to measure the performance of LDMOS are on-resistance and breakdown voltage. The smaller the on-resistance, the better, and the larger the breakdown voltage, the better. In ...

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Problems solved by technology

On the basis of this structure, the on-resistance between the source terminal and the drain terminal of the LDMOS device will be very large, which will reduce the performance of the LDMOS device and affect the application prospect of the LDMOS device.

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