Multi-mode switching circuit and voltage stabilizer

Abstract

The invention provides a multi-mode switching circuit and a voltage stabilizer, and the circuit comprises a pulse generation unit which is used for receiving a first control signal and generating a second control signal and a pulse signal according to the first control signal; a bias unit which is connected with the pulse generation unit and is used for receiving the first control signal and the input voltage and outputting a reference voltage, a first bias voltage and a second bias voltage; an error amplification unit which is connected with the bias unit and the pulse generation unit, and isused for receiving the reference voltage, the first bias voltage and the second bias voltage from the bias unit, receiving the second control signal from the pulse generation unit and then providingan output voltage; a load compensation unit which is connected with the pulse generation unit and the bias unit and used for receiving the second control signal from the pulse generation unit, receiving the first bias voltage and the second bias voltage from the bias unit and providing the minimum load; and a power unit which is connected with the error amplification unit and the load compensationunit and used for providing output voltage. Therefore, overshoot during mode switching is prevented.

Description

technical field [0001] The present application relates to the technical field of voltage regulators, in particular to a multi-mode switching circuit and a voltage regulator. Background technique [0002] Low dropout regulator (LDO) is widely used in System-on-Chip (SoC) and Micro-controller Unit (MCU) to provide stable power to digital or analog circuits. In low-power applications, chips generally have multiple modes, typically at least working mode and standby mode. In the working mode, the chip generally has to process a large amount of data. The digital circuit has a high operating frequency and requires a high supply voltage. At the same time, the current consumed is very large and changes rapidly. At this time, the LDO needs to provide a large supply voltage and high bandwidth. . In standby mode, most components of the chip are in a closed or fixed logic state, only a small number of circuits work at a lower frequency, and a lower power supply voltage can also meet th...

AI Technical Summary

Problems solved by technology

In standby mode, most components of the chip are in a closed or fixed logic state, only a small number of circuits work at a lower frequency, and a lower power supply voltage can also meet the working requirements. The entire chip current is mainly low-frequency low-voltage circuit power consumption and leakage. At this time, the LDO is required to provide a lower supply voltage and a small quiescent current, and the bandwidth of the LDO is not high, but the voltage overshoot will be caused by the sudden change of the load when the mode is switched.

Therefore, it is a very big challenge to design an LDO that meets the requirements of both working mode and standby mode, suppresses the overshoot generated during mode switching, and has high bandwidth and ultra-low power consumption.

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