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System chip hardware Trojan horse detection method and system based on differential amplification controllability

A hardware Trojan detection and differential amplification technology, which is applied in computer parts, character and pattern recognition, internal/peripheral computer component protection, etc., to achieve good detection effect and good concealment characteristics

Active Publication Date: 2020-08-04
FOSHAN POWER SUPPLY BUREAU GUANGDONG POWER GRID
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] The primary purpose of the present invention is to provide a system chip hardware Trojan horse detection method based on the controllability of differential amplification, and to solve the current hardware Trojan horse detection problem in third-party IP and outsourcing design for this detection situation without a reference model

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  • System chip hardware Trojan horse detection method and system based on differential amplification controllability
  • System chip hardware Trojan horse detection method and system based on differential amplification controllability
  • System chip hardware Trojan horse detection method and system based on differential amplification controllability

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Embodiment 1

[0044] This embodiment provides a system chip hardware Trojan horse detection method based on differential amplification controllability, such as figure 1 , including the following steps:

[0045] S1: Obtain the gate-level netlist of the circuit to be tested;

[0046] S2: Obtain the controllability of the signal combination of the circuit under test;

[0047] S3: classify the signals whose combined controllability is greater than the threshold as Trojan horse signals;

[0048] S4: Calculate the differential amplification controllability of the remaining signal;

[0049] S5: Perform kmeans clustering on the differential amplification controllability of the remaining signals;

[0050] S6: Divide the kmeans clustering results into normal signal and Trojan horse signal output.

[0051] In step S1, when obtaining the gate-level netlist of the circuit to be tested for hardware Trojan detection, the RTL-level and gate-level designs are unified and synthesized into a gate-level de...

Embodiment 2

[0065] This embodiment provides a system chip hardware Trojan horse detection system based on differential amplification controllability, such as figure 2 , the detection system application embodiment 1 based on the differential amplification controllability system chip hardware Trojan horse detection method, including:

[0066] A gate-level netlist processing module, the gate-level netlist processing module obtains the gate-level netlist of the circuit to be tested;

[0067] ATPG module, described ATPG module obtains the combined controllability of circuit signal to be tested;

[0068] A signal processing module, wherein the signal processing module classifies signals whose combined controllability is greater than the threshold as Trojan horse signals and calculates the differential amplification controllability of the remaining signals;

[0069] A clustering module, the clustering module performs kmeans clustering on the differential amplification controllability of the re...

Embodiment 3

[0071] This embodiment provides the detection and clustering results of 8 Trojan horse platforms on the Trust-HUB in Embodiment 1, all Trojan horse trigger signals are detected, and the normal signals classified into the Trojan horse signal class are within an acceptable range. Other methods can be used to further confirm whether it is a Trojan horse signal.

[0072] Table 1 gives the image 3 and Figure 4 The 3 types of center points of the corresponding 8 platform clusters, the number of signals of each type, and the class to which the trigger signal is assigned. The trigger signal of the fourth platform is directly classified into the Trojan horse signal category in the signal processing module.

[0073] Table 2 shows the cluster distance and average contour value of each platform. The larger the distance between clusters or the larger the average contour value, it indicates that the clustering effect is better, and the signals can be divided into three obvious categorie...

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Abstract

The invention discloses a system chip hardware Trojan horse detection method and system based on differential amplification controllability. The detection method comprises the following steps of S1, obtaining a gate-level netlist of a to-be-detected circuit; s2, acquiring the controllability of the signal combination of the circuit to be tested; s3, classifying the signals of which the combined controllability is greater than a threshold value into Trojan signals; s4, calculating the differential amplification controllability of the residual signals; s5, carrying out kmeans clustering on the differential amplification controllability of the residual signals; and S6, dividing the kmeans clustering result into a normal signal and a Trojan signal to be output. According to the method, the gate-level netlist is analyzed, and all Trojans inserted before chip manufacturing can be detected theoretically; the combined controllability of the signals in the circuit is analyzed, the controllability of differential amplification is calculated and utilized, the testability of the signals can be reflected, the static overturning probability of the signals can also be reflected, the concealment characteristic of Trojan horses can be better reflected, and a good detection effect is achieved.

Description

technical field [0001] The invention relates to the field of integrated circuit testing, in particular to a system chip hardware Trojan horse detection method and system based on differential amplification controllability. Background technique [0002] With the development of information security technology, the traditional assumption that hardware is the root of trust for security is no longer valid, and the security of hardware itself has become the focus of widespread attention. With the continuous improvement of the integration and complexity of modern ICs, in order to reduce system development costs and speed up product launch time, SoC design methodology based on IP multiplexing technology has gradually become the mainstream mode of ASIC design. The convenience of using third-party IP multiplexing technology comes with the high risk of malicious circuits that may be included in third-party IP, which is the so-called hardware Trojan horse or hardware backdoor. In addit...

Claims

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Application Information

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IPC IPC(8): G06F21/76G06K9/62
CPCG06F21/76G06F18/23213
Inventor 何子兰陈道品倪伟东罗春风武利会陈超雄谭志聪范心明
Owner FOSHAN POWER SUPPLY BUREAU GUANGDONG POWER GRID
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