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System-in-package method and structure of heterogeneous integrated chip

A system-level packaging and integrated chip technology, which is applied in the manufacture of electrical components, electrical solid devices, semiconductor/solid devices, etc., can solve the problems that heterogeneous chips cannot be integrated and packaged, so as to reduce process costs, reduce costs, and reduce process difficulty Effect

Pending Publication Date: 2020-07-24
SHANGHAI XIANFANG SEMICON CO LTD +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] The purpose of the present invention is to provide a system-in-package method and structure for heterogeneous integrated chips to solve the problem that existing heterogeneous chips cannot be integrated and packaged

Method used

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  • System-in-package method and structure of heterogeneous integrated chip
  • System-in-package method and structure of heterogeneous integrated chip
  • System-in-package method and structure of heterogeneous integrated chip

Examples

Experimental program
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Effect test

Embodiment 1

[0048] This embodiment provides a system-in-package method for heterogeneous integrated chips, such as Figure 1-10 As shown, the system-in-package method of the heterogeneous integrated chip includes: making a plurality of silicon substrate chips 10; a plurality of the silicon substrate chips 10 facing away from a carrier 20 and sticking them together on the carrier 20, Form the first integrated adapter plate 101; as figure 2 As shown, a first plastic packaging layer 30 is formed on the first integrated interposer 101, and the silicon substrate chip 10 and the first plastic packaging layer 30 form a first plastic packaging body 102; image 3 As shown, the top of the first plastic package 102 is mechanically or chemically polished, exposing a plurality of electrical leads 11 of the silicon substrate chips 10; Figure 4 As shown, a metal interconnection layer and a dielectric layer 40 are made on top of a plurality of silicon substrate chips 10, and the metal interconnection l...

Embodiment 2

[0060] This embodiment also provides a system-in-package structure of a heterogeneous integrated chip, such as Figure 7 As shown, it includes: a plurality of silicon substrate chips 10; a first plastic sealing layer 30, and the first plastic sealing layer 30 covers the top of the silicon substrate chips 10 and the carrier 20; a plurality of silicon substrate chips 10 The electrical lead-out part 11 is exposed on the top of the first plastic encapsulation layer 30; the metal interconnection layer and the dielectric layer 40 are located on the top of the first plastic encapsulation layer 30, and the metal interconnection layer and the plurality of silicon substrates The electrical lead-out part 11 of the chip 10 is electrically connected; a plurality of heterogeneous chips 50 are located on the top of the metal interconnection layer and the dielectric layer 40 and are electrically connected with the metal interconnection layer and the dielectric layer 40. The heterogeneous chips...

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Abstract

The invention provides a system-in-package method and structure of a heterogeneous integrated chip. The method comprises the steps: enabling bottom surfaces of a plurality of substrate chips to be pasted on slide glass, and forming a first integrated adapter plate; forming a first plastic package layer on the first integrated adapter plate, wherein the substrate chip and the first plastic packagelayer form a first plastic package body; performing a mechanical or chemical polishing process on a top of the first plastic package body to expose electric lead-out parts of the plurality of substrate chips; manufacturing a metal interconnection layer and a dielectric layer on the top surfaces of the plurality of substrate chips, wherein the metal interconnection layer is electrically connected with the electric lead-out parts of the plurality of substrate chips; connecting the plurality of heterogeneous chips to the first integrated adapter plate to form a second integrated adapter plate; performing a mechanical or chemical polishing process on the top of the second integrated adapter plate to enable absolute heights of the plurality of heterogeneous chips to be the same; and removing the first plastic package body from the slide glass.

Description

technical field [0001] The invention relates to the technical field of semiconductor packaging, in particular to a system-level packaging method and structure of a heterogeneous integrated chip. Background technique [0002] With 5G, artificial intelligence (AI), automotive electronics, Internet of Things (IoT), high-efficiency computing (HPC) and other new semiconductor application fields blooming, advanced wafer manufacturing processes are moving towards 7, 5, and 3nm, but as Moore's Law gradually Approaching the physical limit, one of the best ways to prolong the life of Moore's Law is advanced packaging technology, including fan-out wafer-level packaging (FOWLP), 2.5D / 3DIC packaging, and going further into 3D wafer stack packaging capable of heterogeneous integration. SiP packaged modules that meet the needs of heterogeneous integration are bound to have greater energy requirements. [0003] Through-silicon via technology (TSV) realizes the vertical interconnection betw...

Claims

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Application Information

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IPC IPC(8): H01L21/60H01L23/485H01L25/16H01L23/31
CPCH01L25/165H01L23/3114H01L23/3128H01L24/02H01L24/03H01L2224/02331H01L2224/02333H01L2224/02381H01L2224/031H01L2224/16225H01L2924/181H01L2224/73204H01L2224/32225H01L2924/00012H01L2924/00
Inventor 徐成曹立强
Owner SHANGHAI XIANFANG SEMICON CO LTD
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