Multi-stage FPGA wiring method for optimizing time division multiplexing technology

Abstract

The invention relates to a multi-stage FPGA (Field Programmable Gate Array) wiring method for optimizing a time division multiplexing technology. The multi-stage FPGA wiring method comprises the following steps: S1, acquiring an FPGA set, an FPGA connection pair set, a wire network set and a wire network set; S2, according to the FPGA set, the FPGA connection pair set, the wire network set and thewire network set, obtaining the wiring topology of the wire network under the condition that TR is not allocated; S3, allocating a corresponding TR to each edge of each wire network according to different time delay conditions of each wire network group; and S4, circularly carrying out TR reduction and edge legalization, iteratively optimizing the wire network group of which the TR value is greater than a preset value, and obtaining an optimal wiring scheme until an iteration termination condition is met. According to the invention, the problems of inter-chip signal delay and wiring of a multi-FPGA prototype system can be optimized.

Description

technical field [0001] The invention belongs to the technical field of computer-aided design of integrated circuits, and in particular relates to a multi-stage FPGA wiring method for optimizing time-division multiplexing technology. Background technique [0002] Logic verification is an important next step in advanced nanofabrication. During the design process of a system-on-chip, it is estimated that 60% to 80% of the design time of an application-specific integrated circuit (ASIC) is spent in the verification process. Software emulation and hardware emulation are two common logic verification methods, however, software emulation needs to spend a lot of time and cost to simulate each logic gate, and the implementation cost of hardware emulation is relatively high. With the continuous development of the integrated circuit manufacturing process, the scale of the chip is getting larger and larger, and the shortcomings of the above two logic verification methods are becoming m...

AI Technical Summary

Problems solved by technology

This can improve the routability of the entire system, but the delay of the inter-chip signal is increased

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